Fujitsu Series 3 Manual

 
3. Explanation of Operations 
 
3.2.2. Priority conversion operation 
This section explains the priority conversion operation. 
This mode is used to give priority to a specific conversion process. Even when scan conversion is in 
progress, if priority conversion is started, the scan  conversion is interrupted immediately and the priority 
conversion is performed. When the priority conversion  is completed, the scan operation restarts from the 
channel where it was interrupted. If conversion with hi...

 
3. Explanation of Operations 
 
3.2.3. Priority levels and state transitions 
This section explains priority levels and state transitions. 
 Priority levels 
Table 3-1 Priority levels for the A/D converter 
Priority level  Conversion type  Start factor 
1 Priority level 1 conversion 
  Input from external trigger pin (at falling edge) 
2  Priority level 2 conversion  
  Software (when the PSTR bit is set to 1) 
   Trigger input from timer (at rising edge) 
3 Scan conversion  
  Software (when the...

 
3. Explanation of Operations 
 
 State transitions 
Figure 3-5 12-bit A/D converter state transitions 
000
Standby for A/D conversion
010
Priority conversion is in progress.
110
Priority level 1 conversion is in  progress.
Priority level 2 conversion is  pending.
011Priority conversion is in progress.
Scan conversion is  pending.
001
Scan conversion is in progress.
111
Priority level 1 conversion is in progress.
Priority level 2 conversion is pending .
Scan conversion is pending .
Scan conversion...

 
3. Explanation of Operations 
 
3.3. FIFO operations 
The A/D converter has 16 FIFO stages for scan conversion and 4 FIFO stages for priority 
conversion. When conversion data is written in the specified count of FIFO stages, an 
interrupt is generated to the CPU. 
 
3.3.1 FIFO operations in scan conversion 
3.3.2  Interrupts in scan conversion 
3.3.3  FIFO operations in priority conversion 
3.3.4  Interrupts in priority conversion 
3.3.5  Validity of FIFO data 
3.3.6  Bit placement selection for FIFO...

 
3. Explanation of Operations 
 
3.3.1. FIFO operations in scan conversion 
This section explains FIFO operations in scan conversion. 
Sixteen FIFO stages are incorporated for writing scan conversion data. After reset, they are in empty state 
and the SEMP bit in the Scan Conversion Control Register is set to 1. When A/D conversion of one 
channel is completed, the conversion result, start factor , and conversion channel are written in the first FIFO 
stage. This resets SEMP to 0. The conversion resu...

 
3. Explanation of Operations 
 
3.3.2. Interrupts in scan conversion 
This section explains interrupts in scan conversion. 
Figure 3-6 FIFO interrupt settings and FIFO operations 
 
FIFO interrupt 
request FIFO stage 
count settingValid FIFO 
stage count
N=5(6stages)
N=3(4stages)
FIFO readout
A/D conversion
Stop123456Stop123456Stop1 Stop
Flag clear
Flag clear
  
 
When conversion data for the number of FIFO stages (N + 1) set in SFS [3:0] in the Scan Conversion FIFO 
Stage Count Setup Register (SFNS)...

 
3. Explanation of Operations 
 
3. One-shot mode for multiple channels 
To generate an interrupt after the completion of conversion of the multiple specified channels, set the 
FIFO stage count according to the number of channe ls. If eight channels are selected, set the FIFO 
stage count by setting SFS [3:0] = 0x7. When the conv ersion of the last one of the selected channels 
is completed, SCIF is set to 1. 
An interrupt can be generated at any timing before scan completion by setting SFS [3:0] to a...

 
3. Explanation of Operations 
 
3.3.3. FIFO operations in priority conversion 
This section explains FIFO operations in priority conversion. 
Four FIFO stages are incorporated for writing priority conversion data. After reset, they are in empty state 
and the PEMP bit in the Priority Conversion Contro l Register is set to 1. When one A/D conversion 
process is completed, the conversion  result, start factor, and conversion channels are written in the first 
FIFO stage. This resets SEMP to 0. The...

 
3. Explanation of Operations 
 
3.3.4. Interrupts in priority conversion 
This section explains interrupts in priority conversion. 
When conversion data for the number of FIFO stages (N + 1) set in PFS [1:0] in the Priority Conversion 
FIFO Stage Count Setup Register (PFNS) is written in  FIFO, the interrupt request bit (PCIF) in the A/D 
Control Register (ADCR) is set to 1. If the interrupt en able bit (PCIE) is set to 1, an interrupt request is 
generated to the CPU. 
The following explains FIFO...

 
3. Explanation of Operations 
 
3.3.5. Validity  of  FIFO  data 
This section explains restrictions on reading FIFO data registers. 
The bit 12 of the Scan Conversion FIFO Data Register (SCFD) and Priority Conversion FIFO Data Register 
(PCFD) comes with the INVL (A/D conversion result disable) bit which indicates data validity. During 
reading FIFO data registers, the INVL bit is set to 0 if data is valid while the INVL bit is set to 1 if data 
is invalid. 
For word (32 bits) reading, data validity...