Fujitsu Series 3 Manual

 
5. Registers 
 
[bit 11] SCIE: Scan conversion interrupt enable bit This bit controls the interrupt request of SCIF. When the SCIE bit is enabled, and the SCIF bit is set, an 
interrupt request to the CPU is generated. 
Bit Description 
0 Interrupt request disable 
1 Interrupt request enable 
 
[bit 10] PCIE: Priority conversion interrupt enable bit  This bit controls the interrupt request of PCIF. When the PCIE bit is enabled, and the PCIF bit is set, an 
interrupt request to the CPU is generated....

 
5. Registers 
 
5.2.  A/D Status Register (ADSR) 
The A/D Status Register (ADSR) displays scan and priority conversion statuses. 
 bit 7 6 5 4 3 2 1 0 
Field ADSTPFDAS Reserved PCNS PCS SCS 
Attribute R/W  R/W - - - R  R R 
Initial value  0 0  X X X  0 0 0 
 
[bit 7] ADSTP: A/D conversion forced stop bit  Setting the ADSTP bit to 1 stops the A/D conversion operation forcibly (both scan and priority conversion 
operations are stopped). Forced stop of A/D conversion initializes the PCNS, PCS, and SCS...

 
5. Registers 
 
[bit 1] PCS: Priority conversion status flag This flag indicates that priority A/D conversion is in  progress. This flag is set while priority conversion at 
priority level 1 or 2 is performed. Writing is ignored. 
Bit Description 
0  Priority conversion is stopped. 
1 Priority conversion is in progress. 
 
[bit 0] SCS: Scan conversion status flag  This flag indicates that scan A/D conversion is in progress. Writing is ignored. 
Bit Description 
0  Scan conversion is stopped. 
1 Scan...

 
5. Registers 
 
5.3.  Scan Conversion Control Register (SCCR) 
The Scan Conversion Control Register (SCCR) controls the scan conversion mode. 
 bit 15 14 13 12 11 10 9 8 
Field SEMP SFUL SOVR SFCLRReservedRPT SHEN SSTR 
Attribute  R R R/W  R/W - R/W  R/W R/W 
Initial value  1 0 0  0 X  0 0 0 
 
[bit 15] SEMP: Scan conversion FIFO empty bit  This bit is set when FIFO goes to the empty state. Wh en conversion data is written in the Scan Conversion 
FIFO Data Register (SCFD), this b it is set to 0....

 
5. Registers 
 
[bit 11] Reserved: Reserved bit Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 10] RPT: Scan conversion repeat bit  Setting this bit to 1 places the converter in the rep eat mode. When the conversion of all analog input 
channels selected in the Scan Conv ersion Input Selection Register (SCI S) is completed, the conversion is 
started again. 
Setting the RPT bit to 0 ends the repeat conversion . The operation stops when the conversion of the 
analog input...

 
5. Registers 
 
5.4.  Scan Conversion FIFO Stage Count Setup Register (SFNS) 
The Scan Conversion FIFO Stage Count Setup Register (SFNS) sets up the generation of 
interrupt requests in scan conversion. When the specified count of FIFO stages store A/D 
conversion data, the interrupt request bit (SCIF) is set. 
 
bit 7 6 5 4 3 2 1 0 
Field Reserved SFS [3:0] 
Attribute  - - -  - R/W  R/W  R/W R/W 
Initial value  X X X  X 0 0  0 0 
 
[bit 7:4] Reserved: Reserved bits 
Write Has no effect on operation....

 
5. Registers 
 
5.5.  Scan Conversion FIFO Data Register (SCFD) 
The Scan Conversion FIFO Data Register (SCFD) consists of 16 FIFO stages and stores 
analog conversion results. Data can be retrieved sequentially by reading the register. 
 bit 31 30 29 28 27 2625242322212019 18 1716
Field SD11 SD10 SD9  SD8 SD7 SD6SD5SD4SD3SD2SD1SD0Reserved 
Attribute R R R  R R R R R R R R R R R R R 
Initial 
value  X X X X X X X X X X X X X X X X 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved INVL...

 
5. Registers 
 
[bit 4:0] SC4:SC0: Conversion input channel bits The analog input channels corresponding to the conversion result written in SD11 to SD0 are written. 
Settings for channels not defined in the product speci fications are not written. See the specified number of 
the analog input channels in th e Data Sheet of each product. 
Bit [4:0]  Description 
0b00000 ch.0 
0b00001 ch.1 
0b00010 ch.2 
... ... 
0b11101 ch.29 
0b11110 ch.30 
0b11111 ch.31 
 
 
This  reg

ister has different bit...

 
5. Registers 
 
5.6.  Scan Conversion Input Selection Register (SCIS) 
The Scan Conversion Input Selection Register (SCIS) is used to select analog input channels 
for which scan conversion is performed. Any channels can be selected from multiple analog 
inputs. The selected channels are converted in ascending order of channel number. 
 SCIS3 (most significant byte: AN31 to  AN24) and SCIS2 (least significant 
byte: AN23 to AN16) 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field AN31 AN30 AN29 AN28...

 
5. Registers 
 
5.7.  Priority Conversion Control Register (PCCR) 
The Priority Conversion Control Register (PCCR) controls the priority conversion mode. 
Priority conversion can be performed even while scan conversion is being performed. 
In addition, dif ferent prio

rity levels (two levels) can be given to priority conversion processes. 
 bit 15 14 13 12 11 10 9 8 
Field PEMP PFUL POVR PFCLRESCE PEEN PHEN PSTR 
Attribute  R R R/W  R/W R/W R/W  R/W R/W 
Initial value 1 0 0  0 0 0 0 0 
 
[bit 15]...