Fujitsu Series 3 Manual

 
4. Dedicated Baud Rate Generator 
 
4.1.  Baud rate settings 
The following explains how to set the baud rate, and also a result of serial clock frequency 
calculation. 
 Calculating the baud rate 
Two 15-bit reload counters are set using the Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). 
The baud rate is obtained in the following formulas. 
(1) Reload value 
 
(2) Calculation example 
To set the 16MHz bus clock, use the internal clock, and set the 19200-bps baud rate, set the reload 
value...

 
4. Dedicated Baud Rate Generator 
 
 Reload value and baud rate for each bus clock frequency 
Table 4-1 Reload values and baud rates 
8 MHz  10 MHz  16 MHz  20 MHz 24 MHz  32 MHz Baud rate 
(bps) 
Value ERRValue ERR ValueERRValueERRValueERR Value ERR
4 M  - - - - -  0 4 0 5  0 7  0 
2.5 M  - - -  0 - - - - -  - - - 
2 M - 0  4  0 7 0 9 0  11 0 15  0 
1 M  7 0 9 0 15 0 19 0  23 0 31 0 
500000  15 0 19 0 31  0 39  0 47  0 63 0 
460800 - - - - -  - - - 51 -0.16  - - 
250000  31 0 39 0 63  0 79  0 95  0...

 
4. Dedicated Baud Rate Generator 
 
 Allowable baud rate range for data reception 
The following shows the ra nge of baud rate error allowed fo r the destination to receive data. 
Set the reception baud rate error by using the following  formulas to ensure that the value falls within the 
allowable range. 
Figure 4-1 Allowable baud rate range for data reception 
 
  
bit 7
1
bit Stop state
Parity bit 0
Start 
Flmax
bit 7
bit 1 Stop state Parity bit0
Start 
FLmin
Start bit 0 Parity Stop statebit7
bit...

 
4. Dedicated Baud Rate Generator 
 
From the above formulas for obtaining the minimum/maximum baud rate, the allowable error between 
UART and the destination is obtained as follows.   
Reload value (V)Maximum allowable baud rate error Minimum allowable baud rate error
3 0%  0 
10 +2.98% -3.08% 
50 +4.37% -4.40% 
100 +4.56% -4.58% 
200 +4.66% -4.67% 
32767 +4.76% -4.76% 
 
 
Receive accuracy  depe

nds on the number of bits per fra me, bus clock, and reload
  value. The higher the bus 
clock and...

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5.  Setting Procedure and Program Flow in Operation Mode 0 (Async Normal Mode) 
Operation mode 0 enables asynchronous bi-directional serial communications. 
 CPU-to-CPU connection 
Select the bi-directional communication in operation mode 0 (normal mode). Connect two CPUs to each 
other as shown in  Figure 5-1. 
Figure 5-1 A connection example of bi-directional communications in UART operation mode 0 
(with flow control disabled) 
 
CPU_1 (Master)CPU_2 (Slave)
SOT
SIN...

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 Flowcharts 
  If FIFO is not used 
Figure 5-3 An example of bidirectional communication flowchart (if FIFO is not used) 
 
(Transmit side)
Start
Set to the relevant 
operation mode.(Set to mode 0.)
Set the 1-byte data  in TDR and start communication.
RDRF=1
Read and process  the receive data.
(Receive side)
Send data. Start
Set the operation mode.
(So as to have it match  the setting on the transmit side.)
RDRF=1
Read and process the receive data.
Send the 1-byte...

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 If FIFO is used 
Figure 5-4 An example of bidirectional communication flowchart (if FIFO is used) 
 
(Transmit side)
Start
Set the operation 
mode.
(Set to mode 0.)
Set N bytes to transmit  FIFO.
RDRF=1
(Receive side)
Send data. Start
RDRF=1
Yes
Yes
No No
Send back data.
- Enable the transmit/
receive FIFO.
- Setting FBYTE 
Read and process the  FBYTE data.
Set the operation 
mode.
(Set to mode 0.)
Read and process the  FBYTE data.
Set the FDRQ bit to 0.
Set N bytes to...

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6.  Setting Procedure and Program Flow in Operation Mode 1 (Async Multiprocessor Mode) 
In operation mode 1 (multiprocessor mode), co mmunications by master/slave connections 
with multiple CPUs. Either the master or slave function is available. 
 CPU-to-CPU connection 
In a master/slave type communications, as shown in  the figure, the communications system is configured 
with two common communication lines connected to the master CPU and multiple slave CPUs. UART can...

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 Communications procedure 
Communications start when the master CPU transmits address data. Address data is a data set whose D8 bit 
is 1, and used for selecting a slave CPU to co mmunicate with. Each slave CPU judges the address as 
programmed, and communicates  with the master CPU if that address matches the assigned address. 
Figure 6-2  and Figure 6-3  show flowcharts of master/slave type  communications

 (in multiprocessor mode). 
CHAPTER  19-2: UART  \050Async...

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 Flowcharts 
  If FIFO is not used 
Figure 6-2 An example flowchart for master/slave type communications (if FIFO buffer is not used) 
 
(Master CPU)
Start
Set the operation mode 
(set to mode 1).
Set the SIN pin to serial  data input.
Set the SOT pin to serial  data output.
Set 7 or 8 data bits. Set 1 or 2 stop bits.
No No
Set the D8 bit to 1.
Enables transmit/
receive operation.
Transmits the slave  address.
Communicates with a slave CPU.
Set the D8 bit to 0....