Fujitsu Series 3 Manual

 
1. Overview of the Multi-function Serial Interface 
 
CHAPTER: Multi-function Serial Interface 
This chapter describes the overview of the multi-function serial interface. 
 
1.
 Overview of the Multi-function Serial Interface 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFMFS-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-1: Multi-function  Serial Interface 
MN706-00002-1v0-E 
795 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview of the Multi-function Serial Interface 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Multi-function Serial Interface 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  3 
1.  Overview of the Multi-function Serial Interface 
This multi-function serial interface has the following characteristics. 
  Interface Mode 
The following interface modes are  selectable for the multi-function serial interface depending on the 
operation mode settings. 
   UART0 (Asynchronous normal serial interface) 
   UART1...

 
1. Overview of UART (Async Serial Interface) 
 
CHAPTER: UART (Async Serial Interface) 
This chapter explains the UART (async serial interface) function supported in operation mode 
0 and 1 of the multifunctional serial interface. 
 
1.
 Overview of UART (Async Serial Interface) 
2. UART Interrupt 
3. UART Operation 
4. Dedicated Baud Rate Generator 
5. Setting Procedure and Program Flow in Operation Mode 0 (Async Normal Mode) 
6. Setting Procedure and Program Flow in Oper ation Mode 1 (Async...

 
1. Overview of UART (Async Serial Interface) 
 
1.  Overview of UART (Async Serial Interface) 
UART (async serial interface) is a general-purpose serial data communications interface for 
asynchronous communications with external devices. It supports a bi-directional 
communications function (normal mode) and a master/slave type communications function 
(multi-processor mode: both master and slave modes supported). It also has transmit/receive 
FIFO installed.
 
  Functions of UART (Async Serial...

 
2. UART Interrupt 
 
2. UART Interrupt 
UART generates transmit or receive interrupts. These interrupt requests can be generated if: 
- Incoming data is set in the Receive Data Register (RDR) or a data receive error occurs. 
- Outgoing data is transferred from the Transmit Data Register (TDR) to the transmit shif
t 
register and the data transmission is started. 
- The transmit bus is idle (No data transmission occurs). 
- Transmit FIFO data is requested. 
  UART Interrupt 
Ta b l e  2 - 1  shows the...

 
2. UART Interrupt 
 
2.1.  Receive interrupt and flag set timing 
Data reception can be interrupted by a Receive Completion (SSR:RDRF) or a Receive Error 
Occurrence (SSR:PE, ORE, FRE). 
 Receive interrupt and flag set timing   
Upon detection of the first  stop bit, received data are stored in the Receive Data Register (RDR). When the 
data reception is completed (SSR:RDRF=1) or when  a data receive error occurs (SSR:PE, ORE, FRE=1), 
each flag is set. If receive interrupts are enab led (SSR:RIE=1)...

 
2. UART Interrupt 
 
Figure 2-3 ORE (Overrun Error) flag bit set timing 
 
Receive data
RDRFORE
   
ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP
Precautions: - If the next data is transferred before the receive data is read  (RDRF=1), an overrun error occurs.
 
  
  
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-2: UART  \050Async  Serial Interface\051 
MN706-00002-1v0-E 
801 
MB9Axxx/MB9Bxxx  Series  

 
2. UART Interrupt 
 
2.2.  Interrupt and flag set timing when receive FIFO is used 
If the receive FIFO is used, an interrupt occurs when the FBYTE data (preset for the FBYTE 
register) is received. 
 Interrupt and flag set timing  when receive FIFO is used 
If the receive FIFO is used, an interrupt occurs depending on the value set for the FBYTE register.   
  When full FBYTE data is received, the receive data full flag (SSR:RDRF) of the Se rial Status register is 
set to 1. If receive interrupts...

 
2. UART Interrupt 
 
Figure 2-5 ORE (Overrun Error) flag bit set timing 
 
Receive data
FBYTE setting 
(with the transfer count)
RDRF
62nd byte
62
Precautions:
If the next data set is received when the FBYTE reading is indicating the FIFO capacity, 
an overrun error occurs.
This figure shows a case where a 64-byte FIFO capacity is applied.
63rd byte 64th byte 65th byte
STSPST SP STSP ST SP ST66th byteSP
62 64Reading of FBYTE 
(Effective byte count display)
ORE
An overrun error occurred. 
63...

 
2. UART Interrupt 
 
2.3.  Transmit interrupt and flag set timing 
A transmit interrupt occurs when outgoing data is transferred from the Transmit Data Register 
(TDR) to the transmit shift register (SSR:TDRE = 1) and transmission starts and when no 
transmission is performed (SSR:TBI = 1).   
 Transmit interrupt and flag set timing 
  Transmit data empty flag (SSR:TDRE) set timing 
After data has been transferred from the Transmit Data  Register (TDR) to the transmit shift register, the 
next data...