Fujitsu Series 3 Manual

 
3. Explanation of Operations 
 
3.3.6. Bit placement selection for FIFO data registers 
This section explains bit placement selection for FIFO data registers. 
The A/D converter can change the bit placement for the conversion results in the Scan Conversion FIFO 
Data Register (SCFD) and Priority Conversion FIFO Da ta Register (PCFD) with the FDAS bit in the A/D 
Status Register (ADSR) ( Figure 3-7). 
Setting the  FDAS bit to 1 
places 12-bit 

A/D conversion results (SD11 to SD0, PD11 to PD0) on the...

 
3. Explanation of Operations 
 
3.4.  A/D comparison function 
The A/D comparison function compares A/D conversion results and generates interrupts. 
To use the comparison function, set the CMPEN bit in the A/D Comparison Control Register (bit 7 in the 
CMPCR register) to 1. 
The values set in the A/D Comparison Value Setup Register (CMPD) are compared with the most 
significant 10 bits (AD11:2) of the A/D conversion  result. If the comparison result satisfies the conditions 
set in the A/D Comparison...

 
3. Explanation of Operations 
 
3.5. Starting DMA 
The A/D converter can start DMA transfer with a scan conversion FIFO stage count interrupt 
request.  
The A/D converter can transfer scan FIFO data by connecting the interrupt signal of scan conversion from 
the A/D converter to DMA and starting DMA. By setting  the scan FIFO stage count for interrupt generation 
to 0 (an interrupt is generated when a conversion re sult is stored in the first FIFO stage), DMA transfer 
can be performed in conjunction...

 
4. Setup procedure examples 
 
4.  Setup procedure examples 
This section provides examples of setup procedures for the 12-bit A/D converter. 
 
4.1 A/D Operation Enable Setup Procedure Example 
4.2  Scan conversion setup procedure example 
4.3  Priority conversion setup procedure example 
4.4  Setting the conversion time 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-3: 12-bit  A/D Converter 
MN706-00002-1v0-E 
758 
MB9Axxx/MB9Bxxx  Series  

 
4. Setup procedure examples 
 
4.1.  A/D Operation Enable Setup Procedure Example 
This section provides an A/D operation enable setup procedure example. 
Set the period of operation enable state transitions 
 Poll the operation enable state 
Figure 4-1 A/D Operation Enable Setup Procedure Example 
 
  
 
FUJITSU SEMICONDUCT
OR LIMITED 
CHAPTER  18-3: 12-bit  A/D Converter 
MN706-00002-1v0-E 
759 
MB9Axxx/MB9Bxxx  Series  

 
4. Setup procedure examples 
 
4.2.  Scan conversion setup procedure example 
This section provides a scan conversion setup procedure example. 
Scan conversion by software startup 
 Set A/D conversion channels to ch.1 and ch.3 
 Set different sampling times for ch.1 and ch.3 
 Set the comparison time 
 Read the least significant 16 bits of FIFO data and check data validity by the INVL bit 
 After checking that data is valid, read the most significant 16 bits of FIFO data 
Figure 4-2 Scan...

 
4. Setup procedure examples 
 
4.3.  Priority conversion setup procedure example 
This section provides a priority conversion setup procedure example. 
Priority conversion at priority level 2 by timer start 
 Conversion channels are ch.1 and ch.3 
 Set different sampling times for ch.1 and ch.3 
 Set the comparison time 
 Read 32 bits of FIFO data by using an interrupt 
 Read FIFO by the specified stage count   
Figure 4-3 Priority conversion setup procedure example 
 
  
 
FUJITSU...

 
4. Setup procedure examples 
 
4.4.  Setting the conversion time 
The conversion time of the A/D converter is sampling time + comparison time. Two 
sampling time settings can be applied to each channel. This section explains how to set and 
calculate the conversion time. 
 Example of setting the sampling time 
A sampling time is set in each of Sampling Time Setup Registers 0 and 1 (ADST0 and ADST1). Using 
Sampling Time Selection Registers (ADSS3 to 0), whether Sampling Time Setup Registers 0 or 1 is...

 
5. Registers 
 
5. Registers 
This section explains the configuration and functions of the registers used for the \
12-bit A/D 
converter. 
 List of registers for  the 12-bit A/D converter 
Abbreviation Register  name See 
ADCR A/D Control Register  5.1 
ADSR A/D Status Register  5.2 
SCCR Scan Conversion Control Register  5.3 
SFNS Scan Conversion FIFO Stage Count Setup Register  5.4 
SCFD Scan Conversion FIFO Data Register  5.5 
SCIS Scan Conversion Input Selection Register  5.6 
PCCR Priority...

 
5. Registers 
 
5.1.  A/D Control Register (ADCR) 
The A/D Control Register (ADCR) performs interrupt flag display and interrupt enable control. 
 bit 15 14 13 12 11 10 9 8 
Field SCIF PCIF CMPIFRes ervedSCIE PCIE CMPIE OVRIE
Attribute R/W R/W R/W  - R/W R/W  R/W R/W 
Initial value 0 0 0  X 0 0  0 0 
 
[bit 15] SCIF: Scan conversion interrupt request bit  When conversion values are written up to the stage count specified in the Scan Conversion FIFO Stage 
Count Setup Register (SFNS) , this bit is set...