Fujitsu Series 3 Manual

 
3. Explanation of Operations 
 
3.2.3. FIFO operations in priority conversion 
This section explains FIFO operations in priority conversion. 
Four FIFO stages are incorporated for writing priority conversion data. After reset, they are in empty state 
and the PEMP bit in the Priority Conversion Contro l Register is set to 1. When one A/D conversion 
process is completed, the conversion  result, start factor (priority level), and conversion channels are written 
in the first FIFO stage. This resets SEMP...

 
3. Explanation of Operations 
 
3.2.4. Interrupts in priority conversion 
This section explains interrupts in priority conversion. 
When conversion data for the number of FIFO stages (N + 1) set in PFS [1:0] in the Priority Conversion 
FIFO Stage Count Setup Register (PFNS) is written in  FIFO, the interrupt request bit (PCIF) in the A/D 
Control Register (ADCR) is set to 1. If the interrupt en able bit (PCIE) is set to 1, an interrupt request is 
generated to the CPU. 
The following explains FIFO...

 
3. Explanation of Operations 
 
3.2.5. Restrictions on reading FIFO data registers in empty state 
This section explains restrictions on reading FIFO data registers. 
Read SCFD (Scan FIFO Data Register) only when SEMP (scan conversion FIFO empty bit) = 0. Likewise, 
read the PCFD (Priority FIFO Data  Register) only when PEMP (priority conversion FIFO empty bit) = 0. 
If the SCFD or PCFD is read afte r confirming that the SEMP or PEMP  is 1 (FIFO is empty), an A/D 
conversion result may have been stored...

 
3. Explanation of Operations 
 
3.2.6. Bit placement selection for FIFO data registers 
This section explains bit placement selection for FIFO data registers. 
The A/D converter can change the bit placement for the conversion results in the Scan Conversion FIFO 
Data Register (SCFD) and Priority Conversion FIFO Da ta Register (PCFD) with the FDAS bit in the A/D 
Status Register (ADSR). 
The bit placement in the Scan Convers ion FIFO Data Register (SCFD) and Priority Conversion FIFO Data 
Register...

 
3. Explanation of Operations 
 
3.3.  A/D comparison function 
The A/D comparison function compares A/D conversion results and generates interrupts. 
To use the comparison function, set the CMPEN bit in the A/D Comparison Control Register (bit 7 in the 
CMPCR register) to 1. 
The values set in the A/D Comparison Value Setup Register (CMPD) are compared with the most 
significant eight bits (AD9 to 2) of the A/D conver sion result. If the comparison result satisfies the 
conditions set in the A/D...

 
3. Explanation of Operations 
 
3.4. Starting DMA 
The A/D converter can start DMA transfer with a scan conversion FIFO stage count interrupt 
request.  
The A/D converter can transfer scan FIFO data by connecting the interrupt signal of scan conversion from 
the A/D converter to DMA and starting DMA. By settin g the scan FIFO stage count to 0 (an interrupt 
request is generated when a conversion result is stor ed in the first stage of FIFO), DMA transfer can be 
performed in conjunction with A/D...

 
4. Setup procedure examples 
 
4.  Setup procedure examples 
This section provides examples of setup procedures for the 10-bit A/D converter. 
 
4.1 Scan conversion setup procedure example 
4.2  Priority conversion setup procedure example 
4.3  Setting the conversion time 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-2: 10-bit  A/D Converter 
MN706-00002-1v0-E 
711 
MB9Axxx/MB9Bxxx  Series  

 
4. Setup procedure examples 
 
4.1.  Scan conversion setup procedure example 
This section provides a scan conversion setup procedure example. 
Figure 4-1 Scan conversion setup procedure example 
 
Empty check readoutSCCR:SEMP = 0?
Initial settings
- A/D conversion channel  setting (written in the SCIS register)
- Sampling time setting (written in the ADST and ADSS registers)
- Comparison time setting (written in the ADCT register)
- Setting the FIFO stage count to  16 (setting SFNS:SFS = 0b1111)
-...

 
4. Setup procedure examples 
 
4.2.  Priority conversion setup procedure example 
This section provides a priority conversion setup procedure example. 
Figure 4-2 Priority conversion setup procedure example 
 
Empty check readoutPCCR:PEMP = 0?
Initial settings
- A/D conversion channel setting (w ritten in the PCIS register)
- Sampling time setting (written in the ADST and ADSS registers)
- Comparison time setting (written in the ADCT register)
- Setting the FIFO stage count to 4 (setting PFNS:PFS =...

 
4. Setup procedure examples 
 
4.3.  Setting the conversion time 
The conversion time of the A/D converter is sampling time + comparison time. Two 
sampling time settings can be applied to each channel. This section explains how to set and 
calculate the conversion time. 
 Example of setting the sampling time 
A sampling time is set in each of Sampling Time Setup Registers 0 and 1 (ADST0 and ADST1). Using 
Sampling Time Selection Registers (ADSS3 to 0), whether Sampling Time Setup Registers 0 or 1 is...