Fujitsu Series 3 Manual

 
4. Registers 
 
[bit 9:8] PCRM1, PCRM0: Position counter reset mask bits These bits are used to specify the period (mask time) to ignore the events shown below after detecting a 
position counter overflow or underflow or detecting a ZIN active edge. 
  Position counter resetting 
   Revolution counter increment or decrement 
 
This mask function is released when the count direc tion of the position counter is changed, and restarts 
when a position counter overflow or underflow is  detected or a ZIN...

 
4. Registers 
 
4.6.  QPRC Extension Control Register (QECR) 
The QPRC Extension Control Register (QECR) is used to select that the revolution counter is 
inside the count range, indicate that the revolution counter is outside the count range, or 
control whether or not to generate an interrupt when the revolution counter gets out of the 
range. 
 
bit 15 14 1312 11 10 98765432 1 0 
Field Reserved ORNGIE ORNGF ORNGMD
Attribute  - - - - - - ------- R/W R/W  R/W 
Initial 
value  0 0 0 0 0 0 00000000 0 0...

 
4. Registers 
 
[bit 0] ORNGMD: Outrange mode selection bit This bit defines the outrange mode of the revolution counter. 
Bit Description 
0  Selects a positive number (in the  range from 0x0000 to 0xFFFF). 
1 Selects the 8K value (in the range from 0x0000 to 0x7FFFF). 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
677 
MB9Axxx/MB9Bxxx  Series  

 
4. Registers 
 
4.7.  Low-Order Bytes of QPRC Interrupt Control Register 
(QICRL) 
The Low-Order Bytes of QPRC Interrupt Contro l Register (QICRL) are used to control a 
position counter overflow or underflow interrupt, zero index interrupt, QPRC positio\
n counter 
comparison match interrupt, or QPRC position and revolution counter comparison match 
interrupt. 
 
bit 7 6 5 4 3 2 1 0 
Field ZIIF OFDF UFDF OUZIEQPRCMFQPRCMIE QPCMF QPCMIE
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0...

 
4. Registers 
 
[bit 5] UFDF: Underflow interrupt request flag bit This flag indicates that a position counter underflow occurs. When the position counter is counted down, 
this bit is set to 1 if the position counter is 0x0000. 
This flag can only clear to 0 in write mode. Setting 1 has no effect. 
1 is read by the read-modify-write access operation. 
Description Bit  Read Write 
0 Detects no underflow.  Clears this bit. 
1 Detects underflow.  No effect. 
 
[bit 4] OUZIE: Overflow, underflow, or zero...

 
4. Registers 
 
   If the register function selection bit (QCR:RSEL) is  set to 0, the PC and 
 RC match interrupt request 
flag bit (QPRCMF) is set to 1 immediately when  the following one of conditions is satisfied. 
   The mode is changed to PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or 
PC_Mode3 (QCR:PCM[1:0]=11) when the pos ition counter is disabled (QCR:PCM[1:0]=00) 
and the value of the position counter matches that of the QPRC Position and Revolution Counter 
Compare Register...

 
4. Registers 
 
[bit 1] QPCMF: PC match interrupt request flag bit This flag indicates whether or not the value of the position counter matches that of the QPRC Position 
Counter Compare Register (QPCCR). 
This flag is set to 1 if the value of the position counter matches that of the QPRC Position Counter 
Compare Register (QPCCR). 
This flag can only clear to 0 in write mode. Setting 1 has no effect. 
1 is read by the read-modify-write access operation. 
Description Bit  Read Write 
0 Detects no...

 
4. Registers 
 
4.8.  High-Order Bytes of QPRC Interrupt Control Register (QICRH) 
The High-Order Bytes of QPRC Interrupt Control Register (QICRH) are used to control a 
match between the position counter and QPCCR, a match between the revolution counter 
and QPRCR, and a count inversion interrupt. They are also used to indicate the direction of 
the position counter when the last underflow or overflow interrupt was detected or the last 
value of the position counter was changed. 
 
bit 15 14 13 12 11...

 
4. Registers 
 
 The PC match and RC match interrupt request flag bit (QPCNRCMF) is set to 1 immediately when the 
following one of
  conditions is satisfied. 
   The mode is changed to PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or 
PC_Mode3 (QCR:PCM[1:0]=11) when the positio n counter is disabled (QCR:PCM[1:0]=00) and 
the revolution counter is in the mode other than RC_Mode0(QCR:RCM[1:0]=00) while the value 
of the position counter matches that of the QPRC Position Counter Compare...

 
4. Registers 
 
[bit 10] DIRPC: Last position counter direction bit This bit indicates the count direction when the position counter was last changed. 
Bit Description 
0  The position counter was incremented. 
1 The position counter was decremented. 
 
 
As the di rection

 of the position counter is not detected in PC_Mode0 (QCR:PCM[1:0]=00), the last 
position coun ter 

direction bit (QICR:DI RPC) becomes indefinite. Therefore, if the mode is changed from 
PC_Mode0 (QCR:PCM[1:0]=00) to another...