Fujitsu Series 3 Manual

 
5. Registers 
 
[Bit 8] STR0: 8-bit UP counter operation Enable bit This bit enables the 8-bit UP counter operation. 
Bit Function 
Read  0 is always read. 
Writing by 0  No effect 
Writing by 1  Starts the PPG UP counter operation. 
 
[Bits 7:0] RES: Reserved bits  0b00000000 is read from these bits. 
Set these bits to 0b00000000 when writing. 
 
 
  If TRGn O=1

 is set for matching by compare register value and if TRGnO=0 is set simultaneously, the 
start tr i

gger clear operation by TRGnO=0...

 
5. Registers 
 
5.2.  PPG Start Trigger Control Register 1 (TTCR1) 
The TTCR1 Register controls a start of PPG8/PPG10/PPG12/PPG14 Register. 
 Register configuration 
Bit  15 14 13  12 11 10  9 8 
Field TRG7O TRG5O TRG3O TRG1O CS11 CS10 MONI1  STR1 
Attribute  R/W R/W R/W  R/W R/W R/W  R R/W 
Initial value  1 b1 1 b1 1 b1  1 b1  1b0 1b0  1b0 1b0 
           
Bit  7 6 5  4 3 2 1 0 
Field Reserved 
Attribute - 
Initial value  - 
 
  Register functions 
[Bits 15:12] TRG7O, TRG5O, TRG3O,  TRG1O: PPG...

 
5. Registers 
 
[Bit 8] STR1: 8-bit Counter Operation Enable bit This bit enables the 8-bit UP counter operation. 
Bit Function 
Read  0 is always read. 
Writing by 0  No effect 
Writing by 1  Starts the PPG Counter operation. 
 
[Bits 7:0] RES: Reserved bits  0b00000000 is read from these bits. 
Set these bits to 0b00000000 when writing. 
 
 
 
  If TRGn O=1

 is set for matching by compare register value and if TRGnO=0 is set simultaneously, the 
start tr i

gger clear operation by TRGnO=0 setting...

 
5. Registers 
 
5.3.  PPG Compare Register n (COMPn, where n=0 to 7) 
The COMPn Register sets a Compare Register value of the Timing Generator. 
 Register configuration 
Bit  15/7 14/6 13/5  12/4 11/3 10/2  9/1 8/0 
Field COMPn 
Attribute R/W 
Initial value  8b00000000 
Note:  Bits 7 to 0 are set for an odd number address, bu t bits 15 to 8 are set for an even number address. 
 Register functions 
[Bits 15:8, or bits 7:0] COMP7 to CO MP0: Compare Register channels 7 to 0 
Sets a PPG Compare Register...

 
5. Registers 
 
5.4.  PPG Start Register (TRG) 
The TRG Register allows a start of the PPG. 
 Register configuration 
Bit  15 14 13  12 11 10  9 8 
Field  PEN15 PEN14 PEN13  PEN12 PEN11 PEN10  PEN09 PEN08 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1b0 1b0 1b0  1b0 1b0 1b0 1b0 1b0 
           
Bit  7 6 5  4 3 2 1 0 
Field  PEN07 PEN06 PEN05  PEN04 PEN03 PEN02 PEN01 PEN00 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1b0 1b0 1b0  1b0 1b0 1b0 1b0 1b0 
 
  Register functions...

 
5. Registers 
 
5.5.  Output Reverse Register (REVC) 
The REVC Register sets an output polarity of PPG output value. 
 Register configuration 
Bit  15 14 13  12 11 10  9 8 
Field  REV15REV14 REV13 REV12REV11 REV10 REV09 REV08
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1b0 1b0 1b0  1b0 1b0 1b0 1b0 1b0 
           
Bit  7 6 5  4 3 2 1 0 
Field  REV07REV06 REV05 REV04REV03 REV02 REV01 REV00
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1b0 1b0 1b0  1b0 1b0 1b0 1b0 1b0 
 
...

 
5. Registers 
 
5.6.  PPG Operation Mode Control Register (PPGC) 
PPGC Register sets an interrupt, an operation mode, and the prescaler data. 
 PPGC Register configuration list 
  15   8  7    0 Initial 
value  Access  Corresponding 
PPG 
 PPGC0  PPGC1 0x0000R/W PPG0, PPG1 
 PPGC2  PPGC3 0x0000R/W PPG2, PPG3 
 PPGC4  PPGC5 0x0000R/W PPG4, PPG5 
 PPGC6  PPGC7 0x0000R/W PPG6, PPG7 
 PPGC8  PPGC9 0x0000R/W PPG8, PPG9 
 PPGC10  PPGC11 0x0000R/W PPG10, PPG11
 PPGC12  PPGC13 0x0000R/W PPG12, PPG13
 PPGC14...

 
5. Registers 
 
[Bit 12 or 11, or bit 4 or 3] CS1, CS0: PPG DOWN Counter Operation Clock Select bits 
Sets an operation clock of PPGs DOWN Counter. 
Bit 12 or 4  Bit 11 or 3  Function 
0 0 PCLK [Initial  value] 
0 1  PCLK/4 
1 0  PCLK/16 
1 1 PCLK/64 
 
[Bit 10 or 9, or bit 9 or 1] MD1, MD0: PPG Operation Mode Set bits  PPG output value can be set to be reversed. 
Bit 10 or 9  Bit 9 or 1  Function 
0 0 Sets 8-bit operation mode. [Initial value] 
0 1 Sets 8+8-bit operation mode. 
1 0 Sets 16-bit...

 
5. Registers 
 
5.7.  PPG Reload Registers (PRLH, PRLL) 
The PRLH and PRLL Registers set the LOW and HIGH width of PPG. 
 PPGC Register configuration list 
  15   8  7    0 Initial 
value  Access  Corresponding 
PPG 
 PRLH0  PRLL0 0xxxxxR/W  PPG0 
 PRLH1  PRLL1 0xxxxxR/W  PPG1 
 PRLH2  PRLL2 0xxxxxR/W  PPG2 
 PRLH3  PRLL3 0xxxxxR/W  PPG3 
 PRLH4  PRLL4 0xxxxxR/W  PPG4 
 PRLH5  PRLL5 0xxxxxR/W  PPG5 
 PRLH6  PRLL6 0xxxxxR/W  PPG6 
 PRLH7  PRLL7 0xxxxxR/W  PPG7 
 PRLH8  PRLL8 0xxxxxR/W  PPG8 
 PRLH9...

 
5. Registers 
 
 This register operation is determined based on PPG operation mode. 
The following
  defines each operation mode. 
  8-bit operation mode combination 
  15                                  8 7                                   0
 PRLH0  PRLL0 
  Sets the HIGH width of PPG0.  Sets the LOW width of PPG0. 
 PRLH1  PRLL1 
 Sets the HIGH width of PPG1.  Sets the LOW width of PPG1. 
 PRLH2  PRLL2 
 Sets the HIGH width of PPG2.  Sets the LOW width of PPG2. 
 PRLH3  PRLL3 
 Sets the HIGH width...