Fujitsu Series 3 Manual

 
5. Registers 
 
 16+16-bit operation mode combination 
 15                                  87                                   0
 PRLH0 PRLL0 
 Sets the HIGH width of PPG0. 
 PRLH1  PRLL1 
 Sets the LOW width of PPG0. 
 PRLH2  PRLL2 
 Sets the HIGH width of PPG0-pri. 
 PRLH3  PRLL3 
 Sets the LOW width of PPG0-pri. 
  
 
 
 
  Settings of PPGn channel (n=0, 4, 8, or 12) and PPGn+1 channels, PPGn+1 channel, or PPGn+2 channel 
The 16-bit length that combined PRLH with PRLL  bits of PPGn set the...

 
5. Registers 
 
5.8.  PPG Gate Function Control Registers (GATEC0/GATEC4/GATEC4/GATEC8/GATEC12) 
The GATEC Registers specify the start of the PPG using a GATE signal sent from the 
multifunction timer. 
 GATEC Register configuration list 
  15   8  7    0 Initial 
value  Access  Corresponding 
PPG 
 Reserved  GATEC0 0x00 R/W PPG2, PPG0 
 Reserved  GATEC4 0x00 R/W PPG6, PPG4 
 Reserved  GATEC8 0x00 R/W PPG10, PPG8
 Reserved  GATEC12 0x00 R/W PPG14, PPG12
 
 Register configuration (n=0, 4, 8, or 12)...

 
5. Registers 
 
[Bit 1] STRGn: Select trigger bit n (where, n=0, 4, 8, or 12) Selects an operation trigger signal for PPGn. 
Bit Function 
0  Start by the TRG Register setting. [Initial value] 
1 Start by GATE signal from the multifunction timer. 
 
[Bit 0] EDGEn: Start Effective Level Sele ct bit n (where, n=0, 4, 8, or 12) 
Sets an effective level of GATEn signal from the multifunction timer. 
Bit Function 
0  Start at HIGH level. [Initial value] 
1 Start at the LOW level. 
 
FUJITSU SEMICONDUCTOR...

 
6. Notes 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: PPG  
FUJITSU SEMICONDUCTOR CONFIDENTIAL  31  
6. Notes 
This section explains the notes when using the PPG. 
 PPG output operations 
When the PPG is operating, the pulses of LOW period and HIGH level period are continuously output. 
Once the pulse output has started, the PPG does not stop the output until PPG operation is stopped. 
A reset signal must be entered or the PPG stop setting must be set to stop the operation. 
The following explains PPG...

 
1. Overview 
 
Chapter: Quad Position & Revolution Counter 
This chapter explains the functions and operations of the Quad Position & Revolution Counter 
(QPRC). 
 
1.
 Overview 
2. Configuration 
3. Operations 
4. Registers 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FX13-E02.1 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
649 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
The Quad Position & Revolution Counter is used to measure the position of Position Encoder. 
Also, it can be used as an up/down counter by its setting. The Quad Position & Revolution 
Counter contains a 16-bit position counter, a 16-bit revolution counter, two 16-bit compare 
registers, a control register, and its control circuit. 
 Features of Quad Positi on & Revolution Counter 
  The position counter can be operated  in one of the following 3 counting 
modes: 
...

 
2. Configuration 
 
2. Configuration 
The following shows the configuration of Quad Position & Revolution Counter. 
Figure 2-1 Block diagram of Quad Position & Revolution Counter 
 
QPRC Maximum Position Register
Interrupt Generator Circuit
Peripheral buses
Interrupt request
Position Compare Register
Position counter
Control register/QPRC Extension Control 
Register
Interrupt Control Register
Revolution counter
Position and Revolution 
Compare register
Pin swapping
Comparator
Overflow/underflow Reset...

 
3. Operations 
 
3. Operations 
This section explains the operation of Quad Position & Revolution Counter. 
 Operation of position counter 
The position counter receives an input signal from AIN or  BIN external pin as an event of count clock, and 
increments or decrements  the counter. As listed in Table 3-1, the position counter can select a counting 
mode by  setting

 of the position counter mode bits  (QCR:PCM[1:0]) of a control register. The counting 
conditions depend on the selected count...

 
3. Operations 
 
 PC_Mode1: Up/down count mode 
  An external signal entered from  AIN or BIN external pin is receive d as the counting clock, and the 
position counter is counted up or down. 
   In this mode, the position counter is counted up when  an active edge of AIN signal is detected. When an 
active edge of BIN signal is detected, the position counter is counted down. 
 
Figure 3-1 Operations in up/down count mode  (QCR:AES[1:0]=10, QCR:BES[1:0]=10, QCR:SWAP=0) 
 
23432
+1 +1 +1 -1 -1
AIN...

 
3. Operations 
 
 PC_Mode2: Phase difference count mode (supporting the 2-time and 4-time 
frequency multiplication) 
  This mode is useful for counting the difference between phases A and B of encoder output signal. If the 
phase-A and phase-B outputs are re spectively connected to the AIN and BIN pins and if phase A is 
leading phase B, the counter is counted up . If delayed, the counter is counted down. 
   In this mode, when an active edge of AIN signal is  detected, the BIN signal level is...