Fujitsu Series 3 Manual

 
3. Explanation of Operations 
 
3.1. A/D conversion operation 
The A/D converter can perform two types of conversion processes: scan conversion and 
priority conversion. 
 
3.1.1 Scan conversion operation 
3.1.2  Priority conversion operation 
3.1.3  Priority levels and state transitions 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-2: 10-bit  A/D Converter 
MN706-00002-1v0-E 
695 
MB9Axxx/MB9Bxxx  Series  

 
3. Explanation of Operations 
 
3.1.1. Scan conversion operation 
This section explains the scan conversion operation. 
The input channels are selected in the Scan Conversion Input Selection Register (SCIS). By setting the 
corresponding bit in the SCIS to 1, any necessary channel can be selected from among multiple analog 
input channels. 
The A/D converter can be started by software or a timer. To start the converter by software, set the SSTR bit 
in the SCCR register to 1. Then conversion starts. To...

 
3. Explanation of Operations 
 
3. One-shot mode for multiple channels 
This mode is selected when mul tiple analog channels are specified  for scan conversion and RPT = 0 
in the SCCR register. When the conversion starts,  the existence of each channel is automatically 
checked. While the channels are sw itched from one to another, A/D conversion is started and the 
conversion result is written to FIFO when the conversion is completed. The conversion channels are 
selected in descending order of...

 
3. Explanation of Operations 
 
3.1.2. Priority conversion operation 
This section explains the priority conversion operation. 
This mode is used to give priority to a specific conversion process. Even when scan conversion is in 
progress, if priority conversion is started, the scan  conversion is interrupted immediately and the priority 
conversion is performed. When the priority conversion  is completed, the scan operation restarts from the 
channel where it was interrupted. If conversion with hi...

 
3. Explanation of Operations 
 
3.1.3. Priority levels and state transitions 
This section explains priority levels and state transitions. 
 Priority levels 
Table 3-1 Priority levels for the A/D converter 
Priority level  Conversion type  Start factor 
1 Priority level 1 conversion 
  Input from external trigger pin (at falling edge) 
2  Priority level 2 conversion  
  Software (when the PSTR bit is set to 1) 
   Trigger input from timer (at rising edge) 
3 Scan conversion  
  Software (when the...

 
3. Explanation of Operations 
 
 State transitions 
Figure 3-5 10-bit A/D converter state transitions 
000
Standby for A/D conversion
010
Priority conversion is in progress.
110
Priority level 1 conversion is in  progress.
Priority level 2 conversion is  pending.
011Priority conversion is in progress.
Scan conversion is  pending.
001
Scan conversion is in progress.
111
Priority level 1 conversion is in progress.
Priority level 2 conversion is pending .
Scan conversion is pending .
Scan conversion...

 
3. Explanation of Operations 
 
3.2. FIFO operations 
The A/D converter has 16 FIFO stages for scan conversion and 4 FIFO stages for priority 
conversion. When conversion data is written in the specified count of FIFO stages, an 
interrupt is generated to the CPU. 
 
3.2.1 FIFO operations in scan conversion 
3.2.2  Interrupts in scan conversion 
3.2.3  FIFO operations in priority conversion 
3.2.4  Interrupts in priority conversion 
3.2.5  Restrictions on reading FIFO data registers in empty state...

 
3. Explanation of Operations 
 
3.2.1. FIFO operations in scan conversion 
This section explains FIFO operations in scan conversion. 
Sixteen FIFO stages are incorporated for writing scan conversion data. After reset, they are in empty state 
and the SEMP bit in the Scan Conversion Control Register is set to 1. When A/D conversion of one 
channel is completed, the conversion result and conversi on channel are written in the first FIFO stage. This 
resets SEMP to 0. The conversion result and conver sion...

 
3. Explanation of Operations 
 
3.2.2. Interrupts in scan conversion 
This section explains interrupts in scan conversion. 
Figure 3-6 FIFO interrupt settings and FIFO operations 
 
FIFO interrupt 
request FIFO stage 
count settingValid FIFO 
stage count
N=5(6stages)
N=3(4stages)
FIFO readout
A/D conversion
Stop123456Stop123456Stop1 Stop
Flag clear
Flag clear
  
 
When conversion data for the number of FIFO stages (N + 1) set in SFS [3:0] in the Scan Conversion FIFO 
Stage Count Setup Register (SFNS)...

 
3. Explanation of Operations 
 
3. One-shot mode for multiple channels 
To generate an interrupt after the completion of conversion of the multiple specified channels, set the 
FIFO stage count according to the number of channe ls. If eight channels are selected, set the FIFO 
stage count by setting SFS [3:0] = 0x7. When the conv ersion of the last one of the selected channels 
is completed, SCIF is set to 1. 
An interrupt can be generated at any timing before scan completion by setting SFS [3:0] to a...