Fujitsu Series 3 Manual

 
4. Registers 
 
4. Registers 
This section explains the configuration and functions of the registers used for the Quad 
Position & Revolution Counter (QPRC). 
 List of Quad Position & Revolution Counter registers 
 
Abbreviation Register  name See 
QPCR Quad Position & Revolution Counter Position Count Register  4.1 
QRCR QPRC Revolution Count Register  4.2 
QPCCR QPRC Position Counter Compare Register  4.3 
QPRCR QPRC Position and Revolution Counter Compare Register  4.4 
QCR QPRC Control Register...

 
4. Registers 
 
4.1.  Quad Position & Revolution Counter Position Count Register (QPCR) 
The Quad Position & Revolution Counter Position Count Register (QPCR) indicates the 
position counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 
0 
Field QPCR[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit 15:0] QPCR:    Reading this register reads out the current value of  the position counter. While the position counter...

 
4. Registers 
 
   Do not access the Quad Position &  Revolution Counter Position Count R
 egister (QPCR) with a byte 
access instruction. 
   After the count value was written to the Quad Pos ition & Revolution Counter Position Count Register 
(QPCR) while the position counter was unde r suspension (QCR:PSTP=1) in RC_Mode0 
(QCR:RCM[1:0]=00), RC_Mode1 (QCR:RCM[1:0]=01), or RC_Mode3(QCR:RCM[1:0]=11), if a 
ZIN active edge is detected with the count function (QCR:CGSC=0), the Quad Position &...

 
4. Registers 
 
4.2.  QPRC Revolution Count Register (QRCR) 
The QPRC Revolution Count Register (QRCR) indicates the revolution counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 
0 
Field QRCR[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit 15:0] QRCR:    Reading this register reads out th e current value of the revolution counter. While the revolution counter 
stops counting (QCR:RCM[1:0]=00), the count value can...

 
4. Registers 
 
4.3.  QPRC Position Counter Compare Register (QPCCR) 
The QPRC Position Counter Compare Register (QPCCR) is used to compare with the count 
value of the position counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field QPCCR[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit 15:0] QPCCR:    If the value of this register matches that of the po sition counter, the QPRC position counter comparison...

 
4. Registers 
 
4.4.  QPRC Position and Revolution Counter Compare Register (QPRCR) 
The QPRC Position and Revolution Counter Compare Register (QPRCR) is used to compare 
with the selected count value of the position or revolution counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field QPRCR[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit 15:0] QPRCR:    Select whether to compare with the count value of the...

 
4. Registers 
 
4.5.  QPRC Control Register (QCR) 
The QPRC Control Register (QCR) is used to specify the operation mode of the position 
counter or 16-bit revolution counter. It is also used to start or stop each counter. 
 Low-Order Bytes of QPRC Control Register (QCRL) 
 
bit 7 6 5 4 3 2 1 0 
Field SWAP RSEL CGSC PSTP RCM1 RCM0 PCM1 PCM0 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] SWAP: Swap bit  This bit is used to swap the connections of th e AIN input...

 
4. Registers 
 
[bit 5] CGSC: Count clear or gate selection bit This bit is used to select the function of the ZIN external pin. 
When the counter clear function is  enabled (QGSC=0), the ZIN pin clears the position counter if the 
revolution count mode is set to RC_Mode0 (RCM[1:0]=00), RC_Mode1 (RCM[1:0]=01), or 
RC_Mode3 (RCM[1:0]=11). The CGE1 and CGE0 bits  of the QCR register clear the position counter by 
selecting a valid edge of the ZIN pin and detecting the selected edge. 
When the gate...

 
4. Registers 
 
[bit 1:0] PCM1, PCM0: Position counter mode bits These bits are used to select the count mode of the position counter. 
bit1 bit0  Description 
0 0 Disables the position counter (PC_Mode0) to stop it. 
0 1  Up-down count mode (PC_Mode1) 
Increments the value with an AIN active edge and decrements it with a BIN 
active edge. 
1 
0 Phase difference count mode (PC_Mode2) 
Counts up if AIN is leading BIN and down if BIN is leading AIN. 
1  1 Directional count mode (PC_Mode3) 
Counts up or...

 
4. Registers 
 
 High-Order Bytes of QPRC Control Register (QCRH) 
 
bit 15 14 13 12 11 10 9 8 
Field CGE1 CGE0 BES1 BES0 AES1 AES0 PCRM1 PCRM0
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 15:14] CGE1, CGE0: Detection edge selection bits  These bits are used to select the  detection edge when the ZIN external pin is used for the counter clear 
function (CGSC=0). They are also used to select the detection level when the ZIN external pin is used for 
the gate...