Fujitsu Series 3 Manual

 
3. Operations 
 
Table 3-4 Counting in 4-time frequency multiplication mode   (QCR:AES[1:0]=11, QCR:BES[1:0]=11) 
Edge detection pin Detection edge Level Check pinInput level  Counting 
direction  Figure 3-3
Timing 
Rising edge  High Up (1) 
Rising edge  Low Down  (2) 
Falling edge  High Down (3) 
BIN 
Falling edge  AIN 
Low Up (4) 
Rising edge  High Down (5) 
Rising edge  Low Up (6) 
Falling edge  High Up (7) 
AIN 
Falling edge  BIN 
Low Down (8) 
 
Figure 3-3 Operation in 4-time frequency...

 
3. Operations 
 
 PC_Mode3: Count mode with direction 
  A signal entered from the BIN external pin is receive d as the counting clock, and an input level of the 
signal entered form the AIN external pin is used for count direction control for counter up/down 
counting. 
   In this mode, when an active edge of BIN signal is  detected, the AIN signal level is checked and the 
position counter counted up or down. A rising edge, a falling edge, or both can be set as the active edge. 
 
Table 3-5...

 
3. Operations 
 
 Operation of revolution counter 
When the revolution counter receives an input from the ZIN pin (having the counte r clear function) or an 
output of position counter (underflow or overflow), it is  counted up or down. A rising edge, a falling edge, 
or both can be set as the  active edge of ZIN signal. 
The counting conditions of revolution counter depend on the selected mode as follows. 
  RC_Mode0 (QCR:RCM[1:0]=00) 
  The revolution counter is disabled. 
   When the ZIN signal...

 
3. Operations 
 
   When an active edge of ZIN signal and an active edge which counts down position counter are detected 
at the same time duri

ng incrementing of position  counter (QICR:DIRPC=0),  the revolution counter is 
counted down. 
   When an active edge of ZIN signal and an active edge which counts up position counter are detected at 
the same time during decrementing of position c ounter (QICR:DIRPC=1), the revolution counter is 
counted up. 
   When an active edge of ZI N signal, an...

 
3. Operations 
 
Figure 3-8 RC_Mode3 operation (QPRC Maximum Position Register QMPR=9, QCR:CGSC=0) 
 
QPCR23013
2456978 0134
2
ZIN
0
QRCR12
At an active edge of ZIN signal, 
- QPCR is reset.
- QRCR is incremented. When PC overflows, 
- QPCR is reset.
- QRCR is incremented.
  
 
 
  When an  acti

ve edge of ZIN signal and an active edge which counts down position counter are detected 
at the same time du ri

ng incrementing of position  counter (QICR:DIRPC=0),  the revolution counter is 
counted down....

 
3. Operations 
 
 Quad Position & Revolution Counter interrupts   
The following table defines the conditions where an  interrupt request of Quad Position & Revolution 
Counter can generate. 
Table 3-6 Generation conditions of Quad Position & Revolution Counter interrupt requests 
Interrupt request Interrupt request flag  Interrupt request is 
enabled if  Interrupt request is 
cleared if 
Count inversion 
interrupt request  QICR: CDCF=1 QICR: CDCIE=1  QICR:CDCF is set to 
0. 
Zero index interrupt...

 
3. Operations 
 
 Interrupts of position counter 
Figure 3-9 Position counter interrupt timing (RC_Mode0, RC_Mode2 or RC_Mode3) 
 
Time
PC counting
0x0000
QPCCR value
QMPR value
Z input
Count inversion  interrupt
Comparison match  interrupt
Overflow interrupt
Underflow interrupt
Zero index interrupt
  
QPCCR: QPRC Position Counter Compare Register   
 Operation example of QPRC Maximum Position Register (QMPR) interrupt 
The QPRC Maximum Position Register (QMPR) value is  used as the reload data to...

 
3. Operations 
 
During counting up 
When the position counter maximum value overflows to 0x0000, the revolution counter is counted up. 
During this time, the overflow flag (QICRL:OFDF) is set to logical 1. Example: If the QPRC Maximum Position Register (QMPR) is set to 18   
Position counter 15 16 17 18 0 1 2 
Revolution counter  1 1 1 1  2 2 2 
 
During counting down 
When an underflow is detected with 0x0000 and  when the value of Quad Counter Maximum Position 
Counter Register (QMPR) is reloaded to...

 
3. Operations 
 
The following gives an operation example where the position counter reset mask function is used in 
RC_Mode3 (QCR:RCM[1:0]=11). 
Example 1: 
An active edge of ZIN signal is ignored for four (4) counts of position counter after occurrence of 
position counter overflow. 
Figure 3-10 Position counter reset mask operation example 1  (QMPR=99, QCR:PCRM[1:0]=10, QCR:CGSC=0) 
 
QPCR97 98 9902
1345201 3467
5
ZIN
1
QRCR3
2
At an active edge of ZIN signal, 
- QPCR is reset.
- QRCR is...

 
3. Operations 
 
The following gives an operation example where the position counter reset mask function is used in 
RC_Mode0 (QCR:RCM[1:0]=00). 
Example 3: 
An active edge of ZIN signal is ignored for four (4) counts of position counter after occurrence of 
position counter overflow if the revolution counter is disabled. 
Figure 3-12 Position counter reset mask operation example 3  (QMPR=99, QCR:PCRM[1:0]=10, QCR:CGSC=0) 
 
QPCR97 98 9902
1345201 3467
5
ZIN
0
QRCR
At an active edge of ZIN 
signal, the...