Fujitsu Series 3 Manual

 
5. Other Matters 
 
5. Other Matters 
 
5.1 Connection of Model Containing Multiple MFT’s  
5.2  Treatment of Event Detect Register and Interrupt 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
605 
MB9Axxx/MB9Bxxx  Series  

 
5. Other Matters 
 
5.1.  Connection of Model Containing Multiple MFT’s 
This section describes the connection of models that contain multiple MFT’s. 
For models containing more than one multifunction timer unit, the connection of the I/O signals of the 
multifunction timer varies depending on the unit. 
This section describes such connection differences for each multifunction timer unit. 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
606 
MB9Axxx/MB9Bxxx  Series  

 
5. Other Matters 
 
5.1.1. Selection of FRT Connected to OCU and ICU 
OCU and ICU are configured to be able to select FRT for other multifunction timer units. This 
section explains FRT connection between multifunction timer units and the selection method. 
 Model Containing Two MFT’s 
Figure 5-1  shows a diagram of FRT connected between mu ltifunction timer u nits for a model containing 2 
multifunction timer units. 
Figure 5-1 Diagram of FRT Connected between Multifunction Timer Units    (For Model...

 
5. Other Matters 
 
Ta b l e  5 - 1 shows the register settings of OCFS and ICFS of MFT-unit0 and wher e they are connected. 
Table 5-1 OCFS and ICFS Register Settings for MFT-unit0   
(For Model Containing 2 Multifunction Timer Units) 
Register Name Setting Function 
0011  Connects FRT-ch.0 of MFT unti1 to OCU ch.(0). FSO0[3:0]
0100 Connects FRT-ch.1 of MFT unti1 to OCU ch.(0). 
0011 Connects FRT-ch.0 of MFT unti1 to OCU ch.(1). 
OCFS 
FSO1[3:0] 0100 Connects FRT-ch.1 of MFT unti1 to OCU ch.(1). 
0011...

 
5. Other Matters 
 
5.1.2. PPG Timer Unit Connected to WFG 
The PPG timer unit to be connected to WFG varies depending on the multifunction timer unit 
used. This section explains the connection of the PPG timer unit and the selection method. 
 MFT-unit1 
PPG timer unit ch.8, ch.10 and  ch.12 are connected to WFG of MFTunit1, as shown in  Figure 5-2. 
Figure 5-2 Diagram of WFG-PPG Connection at MFTunit1 
 
SEL
SEL
SEL
PPG8
CH10_PPG
CH54_PPG CH54_GATECH32_GATE CH10_GATEGATE8
CH32_PPG
WFSA10.PSEL[1:0]...

 
5. Other Matters 
 
5.2.  Treatment of Event Detect Register and Interrupt 
This section provides notes on the event detect register in the multifunction timer unit, the 
operation and control of interrupt-related circuits. 
 Configuration of Circuit 
Figure 5-3  shows the configuration of th e interru pt signal generator. 
Figure 5-3 Configuration of Interrupt Signal Generator 
 
Interrupt enable
register
Event detectregister
Interrupt signal
（To:Interrupt controller ）
Read value （To:CPU）
Read vaule...

 
5. Other Matters 
 
 Returning from Interrupt Processing 
When an interrupt is processed using an interrupt sign al, it is necessary to clear the event detect register 
when returning from the interrupt processing, deasse rt the interrupt signal, and then return from the 
interrupt. Returning from an interrupt without deasse rting the interrupt signal will result in the same 
interrupt process taking place again w ith no way out of that process. 
 Value Written to Event Detect Register 
The write...

 
5. Other Matters 
 
 Read Value Mask Function at RMW Access 
Since the above procedure is complicated, a masking function is provided to mask the read value of the 
event detect register to 1 at RMW  access for the value to be written back. 
In this model, RMW access occurs, when write  access is made to the bit-banding alias area. 
Write access to the bit-banding alias area is the RMW acces s used to read all of ther register bits in the 
address area where the target bit exists, rewrite only the...

 
5. Other Matters 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Multifunction Timer 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  120 
Table 5-3 List of Event Detect Registers and Interrupt Enable Registers  Block Name Target Event  Event Detect 
Register  Interrupt 
Enable 
Register  Name of Interrupt Signal
FRT ch.0 
Detection of FRT0 == 0x0000 TCSA0.IRQZFTCSA0.IRQZE Zero value detection interrupt
FRT ch.1 Detection of FRT1 == 0x0000 TCSA1.IRQZFTCSA1.IRQZE Zero value detection interrupt
FRT ch.2 Detection of FRT2...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
614 
MB9Axxx/MB9Bxxx  Series