Fujitsu Series 3 Manual

 
4. Registers of Multifunction Timer 
 
4.3.21.  ADCMP Compare Value Store Register, Down-count Direction Only (ACCPDN) 
ACCPDN is a 16-bit register that specifies the timing of starting AD conversion at ADCMP as 
the compare value of the FRT count value. 
Each mounted channel has three registers: ACCPDN0, ACCPDN1 and ACCPDN2. 
ACCPDN0 stores the compare value of ADCMP ch0. 
ACCPDN1 stores the compare value of ADCMP ch1. 
ACCPDN2 stores the compare value of ADCMP ch2. 
It should be noted that this...

 
4. Registers of Multifunction Timer 
 
During FRT’s count operation, the timing of starting AD conversion can be changed by rewriting to this 
register. When the buffer function is disabled, the written value can be immediately reflected on the 
ACCPDN register. When the buffer function is enable d, the settings in the ACCPDN register for multiple 
channels can be synchronized.   
If data is read from this address area, the value in the ACCPDN register is read, rather than the value in the 
buffer...

 
4. Registers of Multifunction Timer 
 
4.3.22.  ADC Start Trigger Select Register (ATSA) 
ATSA is a 16-bit register that selects ADC’s start signal which is output from MFT. 
This register is used to select a start trigger for ADCunit0, unit1 and unit2. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
Bit  15 14 13  12 11 10  9 8 
Field  Reserved  AD2P AD1P AD0P 
Attribute - R/W R/W R/W 
Initial Value  - 0 0 0 0  0 0 
           
Bit  7 6 5  4 3 2 1 0...

 
4. Registers of Multifunction Timer 
 
ATSA.AD0S[1:0] is a register that selects the start signal to be used to start the scan conversion of ADC unit0. 
ATSA.AD1S[1:0] is a register that selects the start signal to be used to start the scan conversion of ADC unit1. 
ATSA.AD2S[1:0] is a register that selects the start signal to be used to start the scan conversion of ADC unit2. 
The starting method used for ADC’s scan conversion start signal that is output from MFT can be selected 
from starting by...

 
4. Registers of Multifunction Timer 
 
ATSA.AD0P[1:0] is a register that selects the start signal to be us ed to start priority conversion of ADC 
unit0. 
ATSA.AD1P[1:0] is a register  that selects the start signal to be us ed to start priority conversion of ADC 
unit1. 
ATSA.AD2P[1:0] is a register  that selects the start signal to be us ed to start priority conversion of ADC 
unit2. 
The starting method used for ADC’s priority conversion st art signal that is output from MFT can be selected 
from...

 
4. Registers of Multifunction Timer 
 
4.4.  Details of OCU Output Waveform 
This section provides details of the output waveform of the RT output signal in each mode of 
OCU. 
 List of OCU Operation Modes 
The operation modes of the OCU are select ed by the following register settings. Table 4-6  shows a list of 
register setting values an
d the operatio n modes of OCU-ch.(0) and OCU-ch.(1). 
Table 4-6 Register Setting Values and the Operation Modes of OCU-ch.(0) and OCU-ch.(1) 
Register Setting...

 
4. Registers of Multifunction Timer 
 
Table 4-7 Details of OCU-ch.(0) Operation and RT(0) Signal Outputs 
OCCP(0) value 
Other than 0x0000 & 0xFFFF   Name of Operation Mode 0x0000 0xFFFF 
Up Peak Down 
Up-count mode (1-change) M:Rev 
U:No M:Rev 
U:No M:Rev 
U:No  M:Rev 
U:No 
- 
Up/Down-count mode (Active High) All-Act All-Ina M:Act 
U:No  M:Ina 
U:No 
Up/Down-count mode (Active Low) All-Act All-Ina M:Act 
U:No M:No 
U:No 
(*7) 
M:Ina 
U:No 
 
Table 4-8 Details of OCU-ch.(1) Operation and RT(1) Signal...

 
4. Registers of Multifunction Timer 
 
 Up-count Mode (1-change) 
When Up-count mode (1-change) is selected, the following operation applies. 
Regardless of FRT’s count state, the output level of the RT(0) signal is reversed when FRT’s count value 
matches OCCP(0). 
Regardless of FRT’s count state, the output level of the RT(1) signal is reversed when FRT’s count value 
matches OCCP(1). 
In this mode, OCU-ch.(0) and ch.(1) can operate inde pendently from each other. 
Figure 4-14  shows an example of...

 
4. Registers of Multifunction Timer 
 
 Up-count Mode (2-change) 
When Up-count mode (2-change) is selected, the following operation applies. 
Regardless of FRT’s count state, the output level of the RT(1) signal is reversed when FRT’s count value 
matches OCCP(0) or OCCP(1). 
This mode can be used only by OCU ch.(1), not by ch.(0). Also, as OCU-ch.(0) and ch.(1) perform 
interlocked operation, they cannot operate independently from each other. If 2-change mode is selected for 
OCU-ch(1), OCU-ch.(0)...

 
4. Registers of Multifunction Timer 
 
Figure 4-15 shows Example 1 of the operation waveform when OCU-ch.1 is in Up-count mode (2-change). 
This figure is based on  the conditions that the buffer  function of the OCCP1 register is enabled and Zero 
value transfer is set. 
Figure 4-16  shows Example 2 of the operation waveform when OCU-ch.1 is in Up-count mode (2-change). 
Th is figure is based on

 the conditions that the buffer  function of the OCCP1 register is enabled and Peak 
value transfer is...