Fujitsu Series 3 Manual

 
4. Registers of Multifunction Timer 
 
 Always follow the procedure below and perform control when starting PWM signal output by OCU. 
1. Initial setting 
Set FRT 

operation mode (FRT control register other than TCSA.STOP). 
Set OCU operation mode and initialize the output leve l (OCU control register other than OCSA.CST0 
and OCSA.CST1). 
Set the OCCP compare value (writing the OCCP value). 
2.  Start FRT count operation (writing 0 to TCSA.STOP). 
3.  Enable OCU’s operation (writing 1 to OCSB.CST0...

 
4. Registers of Multifunction Timer 
 
[bit4] OCSA.IOE0 
Process Value Function 
0 Does not generate interrupt, when 1 is set to OCSA.IOP0. Write 
1 Generates interrupt, when 1 is set to OCSA.IOP0. 
Read - Reads the register setting. 
 
[bit5] OCSA.IOE1 
Process Value  Function 
0 Does not generate interrupt, when 1 is set to OCSA.IOP1. Write 
1 Generates interrupt, when 1 is set to OCSA.IOP1. 
Read - Reads the register setting. 
 
OCSA.IOE0 is a register that specifies whether to notif y CPU of the...

 
4. Registers of Multifunction Timer 
 
By reading from this register, whether FRT’s count value has reached the OCCP value or not can be 
determined. 
This register can be cleared by writing 0. 
This register does nothing, if 1 is written. Always  write 1 to the register when rewriting to another 
register in the same address area. 
1 is always read from this register at RMW access. 
See  5.2 Treatment of Event Detect Register and Interrupt . 
 
When  

FRT is in Up/Down-count mode, these registers are...

 
4. Registers of Multifunction Timer 
 
4.3.7. OCU Control Register B (OCSB) 
OCSB is an 8-bit register that controls OCU’s operation. 
Each mounted channel has three registers: OCSB10, OCSB32 and OCSB54. 
OCSB10 controls OCU ch1 and OCU ch0. 
OCSB32 controls OCU ch3 and OCU ch2. 
OCSB54 controls OCU ch5 and OCU ch4. 
 Configuration of Register 
 
Bit 15 14 13 12 11 10 9 8 
Field Reserved BTS1 BTS0 CMODReservedReserved OTD1 OTD0 
Attribute  - R/W  R/W R/W -  - R/W  R/W 
Initial Value  - 1  1 0 -  - 0...

 
4. Registers of Multifunction Timer 
 
   After being processed by WFG, OCU’s output pins (RT0 to RT5) become LSI’s external output pins 
(RTO0 to

 RTO5). For this reason, the level of OCU’s output pins does not match the level of LSI’s 
external output pins in some of WFG’s operation modes; therefore care must be taken. The state of LSI’s 
external output pins can be read from the PDIR register of the I/O port block. 
   Follow the procedure below to set the output level to Low by stopping OCU’s...

 
4. Registers of Multifunction Timer 
 
[bit13] OCSB.BTS0 
Process Value Function 
0 Performs buffer transfer of the OCCP(0) register upon Zero value detection 
by FRT. 
Write 
1 Performs buffer transfer of the OCCP(0) register upon Peak value detection 
by FRT. 
Read 
- Reads the register setting. 
 
[bit14] OCSB.BTS1 
Process Value  Function 
0 Performs buffer transfer of the OCCP(1) register upon Zero value detection 
by FRT.     
Write 
1 Performs buffer transfer of the OCCP(1) register upon Peak...

 
4. Registers of Multifunction Timer 
 
4.3.8. OCU Control Register C (OCSC) 
OCSC is an 8-bit register that controls OCU’s operation. 
This register controls all of OCU ch0 to ch.5. 
 Configuration of Register 
B i
t 
15  14 
13 12 
1
 1 
10  9 8 
Field  ReservedReserved  MOD5 MOD4  MOD3 MOD2 MOD1  MOD0 
Attribute - - R/W R/W  R/W R/W R/W  R/W 
Initial Value - - 0 0  0 0 0  0 
 
  Functions of Register 
[bit5:0] OCSC.MOD5, OCSC.M OD4, OCSC.MOD3, OCSC.MOD 2, OCSC.MOD1, OCSC.MOD0 
Process Value...

 
4. Registers of Multifunction Timer 
 
4.3.9. OCU Compare Value Store Register (OCCP) 
OCCP is a 16-bit register that specifies the timing of changing OCU’s output signal as the 
compare value of FRT’s count value. 
Each mounted channel has six registers: OCCP0 to OCCP5. 
OCCP0 stores the compare value of OCU ch.0 (2-change mode, ch.1 compare value). 
OCCP1 stores the compare value of OCU ch.1. 
OCCP2 stores the compare value of OCU ch.2 (2-change mode, ch.3 compare value). 
OCCP3 stores the compare...

 
4. Registers of Multifunction Timer 
 
If 0x0000 or 0xFFFF is written to this register when FRT is in Up/Down-count mode, a fixed value can 
be output. For details, see  4.4 Details of OCU Output Waveform . 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
553 
MB9Axxx/MB9Bxxx  Series  

 
4. Registers of Multifunction Timer 
 
4.3.10.  WFG Control Register A (WFSA) 
WFSA is a 16-bit register that controls WFG’s operation. 
Each mounted channel has three registers: WFSA10, WFSA32 and WFSA54. 
WFSA10 controls WFG ch.10 (the output processing block of OCU ch.1 and OCU ch.0). 
WFSA32 controls WFG ch.32 (the output processing block of OCU ch.3 and OCU ch.2). 
WFSA54 controls WFG ch.54 (the output processing block of OCU ch.5 and OCU ch.4). 
It should be noted that this register does not...