Fujitsu Series 3 Manual

 
2. Configuration of Multifunction Timer 
 
2.3.  I/O Pins of Multifunction Timer Unit 
 Correspondence with LSI External I/O Pins   
Of all the I/O signals illustrated in the block diagrams,  Ta b l e  2 - 1 shows a list of correspondence between 
I/O pins of M
FT unit and LSI external I/O pins. In this series, some models have more than one MFT unit. 
Therefore, LSI pin names are composed of I/O pin names shown in the block diagrams plus MFT’s unit 
number (0, 1, 2). It should be noted that...

 
2. Configuration of Multifunction Timer 
 
 Interrupt Signal Outputs 
Of all the I/O signals illustrated in the block diagrams,  Ta b l e  2 - 2 shows a list of interrupt signals generated 
from the MFT u
nit. Any model that contains more than one MFT unit has interrupt outputs equivalent to the 
number of mounted MFT units. 
Table 2-2 List of Interrupt Signals Generated from MFT Unit 
Generation Block Interrupt Type 
FRT ch.0  Zero value detection interrupt 
FRT ch.1 Zero value detection interrupt...

 
2. Configuration of Multifunction Timer 
 
 Other I/O Signals 
Of all the I/O signals illustrated in the block diagrams, the following section describes the other signals. 
  PCLK 
This is an LSI internal peripheral clock signal used in the MFT unit. It uses the clock signal of the APB bus 
to be connected. FRT (when the LSI internal peripheral  clock is selected) and the WFG timer operate based 
on the count clock divided from PCLK. 
  FRT input and FRT output of external MFT 
A model containing...

 
3. Operations of Multifunction Timer 
 
3.  Operations of Multifunction Timer 
This chapter provides examples of operations of the multifunction timer and explains its 
setting procedures. 
 
3.1 Example of Operation of Multifunction Timer - 1  
3.2  Example of Operation of Multifunction Timer - 2 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
508 
MB9Axxx/MB9Bxxx  Series  

 
3. Operations of Multifunction Timer 
 
3.1.  Example of Operation of Multifunction Timer - 1 
Example of Operation of Multifunction Timer - 1 explains the cases where each function 
block is operated in the following modes: FRT  :  Up-count mode, without interrupt 
OCU  :  Up-count mode (1-change), with interrupt 
WFG  :  RT-PPG mode, generation of GATE signal, superimposition of PPG signal 
ICU  :  Rising edge detection mode, with interrupt 
 Time Chart 
 
Figure 3-1 Time Chart of Main Registers and...

 
3. Operations of Multifunction Timer 
 
 Operation of FRT, OCU 
Timing 1 
  Set Up-count operation to FRT-ch.0 (TCSA0 register write). 
   Set an operating cycle to FRT-ch.0  (TCCP0 register write). In this example, 0x5FFF is set. When the 
pre-scaler is set to 1/128 and PCLK to 40MHz, the count cycle of FRT is 78.6432ms. 
   Connect and set FRT-ch.0 to OCU-ch.0/ch.1 (OCFS10 register write). 
   Set OCU-ch.0/ch.1 to Up-count mode (1-change) operation. Also specify the initial output level of...

 
3. Operations of Multifunction Timer 
 
Timing 5   When the RT0 signal is changed to the Low level, WFG deasserts the GATE signal and gives a stop 
instruction. 
   PPG-ch.0 changes the PPG signal to the Low level and stops the output. 
   WFG changes the RTO0 signal to the Low level and stops the output. 
WFG performs the same operation to the RT1 signal from OCU-ch.1, and superimposes and outputs the 
PPG signal to RTO1. DC chopper control waveform, as shown in the figure, can be output to...

 
3. Operations of Multifunction Timer 
 
Table 3-1 Example of Operation 1 – Register Settings 1 
Setting 
Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
CLK[3:0]0111 Clock division pre-scaler setting: 1/128 
SCLR  0 Soft clear: Do nothing 
MODE  0 Count mode setting: Up-count mode 
STOP  1 FRT count operation: Stop counting 
BFE  1 TCCP buffer function: Enable 
ICRE  0 Peak value detection interrupt: Disable 
ICLR  0 Peak value detection: Clear...

 
3. Operations of Multifunction Timer 
 
Table 3-2 Example of Operation 1 – Register Settings 2 
Setting 
Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
DCK[2:0] 000 Clock division pre-scaler setting: 1/1 (don’t care) 
TMD[2:0] 001 Operation mode : Select RT-PPG mode 
GTEN[1:0] 11 Gate signal genera tion: RT0, RT1 signal logic OR 
PSEL[1:0]00 Connecting PPG : PPG0 
PGEN[1:0] 11  PPG reflection: Logic 
AND of PPG signal to 
RTO0/RTO1 signals 
DMOD  0...

 
3. Operations of Multifunction Timer 
 
Table 3-3 Example of Operation 1 – Register Settings 3 
Setting Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
CST0 DC ch.0 operation state: 
CST1  DC ch.1 operation state: 
BDIS0  DC ch.0 OCCP buffer function: 
BDIS1  DC ch.1 OCCP buffer function: 
IOE0 DC  ch.0 interrupt:  
IOE1 DC ch.1 interrupt: 
IOP0 1 ch.0 match dete ction: Match detected 
OCSA10BR 
IOP1  0 ch.1 match detec tion: Match not detected 
OCCP0...