Fujitsu Series 3 Manual

 
4. Registers of Multifunction Timer 
 
4.1.  Individual Notation and Common Notation of Channel Numbers in Descriptions of Functions 
This section explains the individual notation and common notation of channel numbers in 
descriptions of the functions in this chapter. 
As the multifunction timer unit contains multiple blocks  of the same function and consists of multiple 
channel circuits, there are some common matters across the channels.   
Where there is no need to distinguish among the  channels,...

 
4. Registers of Multifunction Timer 
 
Examples 5 to 8 are examples of the individual notation that clearly identifies the correspondence between 
the control bit and the channel in the control registers by stating two channel numbers in the control register 
(ICFS). 
Example 9:  ICFS.FSI0[3:0] is a register  that selects FRT to be connected to ICU-ch.(0). 
Example 10:  ICFS.FSI1[3:0] is a register  that selects FRT to be connected to ICU-ch.(1). 
Examples 9 and 10 are examples of the common notation...

 
4. Registers of Multifunction Timer 
 
4.2.  List of Registers of Multifunction Timer 
This section provides a list of the registers that exist in the multifunction timer unit. 
Ta b l e  4 - 4 shows a list of the registers that ex ist in the mult ifunction timer unit. 
The control registers of the multifunction timer unit are in the same configuration across the mounted 
channels. In this section, the operation of registers of the same function is explained using the common 
notation. The List of...

 
4. Registers of Multifunction Timer 
 
 Block 
Name  Register 
Name 
(Individual  Notation)  Register Function 
Bit 
Width Acces
s  See  Register Name 
(Common Notation)
WFSA10  WFG ch.10 control register A 
WFSA32 WFG ch.32 control register A 
WFSA54 WFG ch.54 control register A  16
H 4.3.10 WFSA 
WFTM10  WFG ch.10 timer value register 
WFTM32 WFG ch.32 timer value register 
WFG 
WFTM54 WFG ch.54 timer value register  16H 
4.3.11 WFTM 
NZCL NZCL control register  16H 4.3.12 NZCL NZCL 
WFIR Interrupt...

 
4. Registers of Multifunction Timer 
 
4.3.  Details of Register Functions 
This section explains details of the registers that exist in the multifunction timer unit. 
4.3.1  FRT Control Register A (TCSA)  
4.3.2   FRT Control Register B (TCSB)  
4.3.3   FRT Cycle Setting Register (TCCP)  
4.3.4   FRT Count Value Register (TCDT)  
4.3.5   OCU Connecting FRT Select Register (OCFS)  
4.3.6   OCU Control Register A (OCSA)  
4.3.7   OCU Control Register B (OCSB)  
4.3.8   OCU Control Register C (OCSC)...

 
4. Registers of Multifunction Timer 
 
4.3.1. FRT Control Register A (TCSA) 
TCSA is a 16-bit register that controls FRT. 
Each mounted channel has three registers: TCSA0, TCSA1 and TCSA2. 
TCSA0 controls FRT-ch.0. 
TCSA1 controls FRT-ch.1. 
TCSA2 controls FRT-ch.2. 
 Configuration of Register 
Bit  15 14 13  12 11 10  9 8 
Field ECKE  IRQZF IRQZE  Reserved  ICLR ICRE 
Attribute  R/W R/W R/W  - R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field BFE  STOP MODE  SCLR...

 
4. Registers of Multifunction Timer 
 
The following table shows examples of CLK[3:0] settings and FRT count clock cycles. 
FRT Count Clock Cycle 
CLK[3:0] Clock 
Ratio  PCLK=25ns 
(40MHz)  PCLK=33.3ns 
(33MHz)  PCLK=50ns 
(25MHz) 
0000  1  25ns 30ns 50ns 
0001 2  50ns 61ns 100ns 
0010 4  100ns 121ns 200ns 
0011 8  200ns 242ns 400ns 
0100 16  400ns 485ns 800ns 
0101 32  800ns 970ns  1.6μs 
0110 64  1.6μs 1.9 μs 3.2 μs 
0111 128  3.2μs 3.9 μs 6.4 μs 
1000 256  6.4μs 7.8 μs 12.8 μs 
 
[bit4] TCSA.SCLR...

 
4. Registers of Multifunction Timer 
 
[bit5] TCSA.MODE 
Process Value Function 
0 Sets FRT’s count mode to Up-count mode. Write 
1 Sets FRT’s count mode to Up/Down-count mode. 
Read - Read the register setting. 
 
TCSA.MODE is a register that selects FRT’s count mode. 
Change the setting of this register while FRT is stopping. 
In Up-count mode, FRT performs the following operation. 
FRT’s counter starts Up-count operation from 0x0000 . After up-counting to the value set by the TCCP 
register, the...

 
4. Registers of Multifunction Timer 
 
In Up/Down-count mode, FRT performs the following operation. 
FRT’s counter starts Up-count operation from 0x0000. After up-counting to the value set by the TCCP 
register, it starts Down-count operation. When it return s to 0x0000, it starts up-counting again and repeats 
the count operation. FRT’s count cycle is (TCCP) x 2 x Count clock cycle. 
Change in the value of FRT’s counter is shown below. 
0x0000 (Zero value)  
0x0001   
0x0002   ・  
  
・  
(Up-count)...

 
4. Registers of Multifunction Timer 
 
[bit6] TCSA.STOP 
Process Value Function 
0 Puts FRT in operating state. Write 
1 Puts FRT in stopping state. 
Read - Reads the register setting 
 
TCSA.STOP is a register that controls  the start and stop of FRT’s operation. 
This register is used in the combina tion with TCSA.SCLR, as shown below. 
1.  When starting FRT’s counter operation:   
When 0 is written to TCSA.STOP and TCSA.SCLR while FRT’s count operation is stopped, FRT 
starts counting. 
2.  When...