Fujitsu Series 3 Manual

 
9. Descriptions of base timer functions 
 
 Pulse width measurement operation flowchart 
Figure 9-19 Pulse width measurement operation flowchart 
 
  
PWC mode selection
Count clock selection
Operation/ measurement 
mode selection
Interrupt flag clea
r
Interrupt enable
Settings
Start by the CTEN bit
Clearing of the counter
Restart 
One- shot measurement 
mode
 
Continuous 
measurement mode
Measurement start edge 
detection
 
Measurement start edge detection
 
Start of count operation Start of count...

 
9. Descriptions of base timer functions 
 
9.4.2. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PWC 
timer is selected 
The Timer Control Register (TMCR) controls timer operations. 
 Timer Control Register (H igh-order bytes of TMCR) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS2 CKS1 CKS0 res EGS2 EGS1 EGS0 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 15] res: Reserved bit  The read value is 0. 
Set 0 to this bit....

 
9. Descriptions of base timer functions 
 
[bit 10:8] EGS2 to EGS0: Measurement edge selection bits   These bit set measurement edge conditions. 
   Changes to EGS2, EGS1, or EGS0 must be made when the counting is stopped (CTEN = 0). However, 
it is possible to make changes at the same time you set 1 to the CTEN bit. 
Bit 10  Bit 9 Bit 8  Description 
0 0 0  HIGH pulse width measurement ( ↑ to  ↓) 
0  0 1  Cycle measurement between rising edges ( ↑ to  ↑) 
0  1 0  Cycle measurement between falling...

 
9. Descriptions of base timer functions 
 
 Timer Control Register (L ow-order bytes of TMCR) 
 
bit 7 6 5 4 3 2 1 0 
Field T32 FMD2 FMD1 FM D0 res MDSE CTEN res 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] T32: 32-bit timer selection bit    This bit selects the 32-bit timer function. 
   When the FMD2, FMD1, and FMD0 bits are set to 0b100 to select the PWC function, setting the T32 
bit to 1 selects 32-bit PWC mode. 
   Changes must be made while the timer...

 
9. Descriptions of base timer functions 
 
[bit 2] MDSE: Mode selection bit   Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make 
changes at the same time you set 1 to the CTEN bit. 
Bit Description 
0  Continuous measurement mode (Buffer register enabled) 
1 One-shot measurement mode (Stops after one measurement) 
 
[bit 1] CTEN: Timer enable bit    This bit enables the start or  restart of the up counter. 
   When the counter is in operation en abled status...

 
9. Descriptions of base timer functions 
 
 Timer Control Register 2 (High-order bytes of TMCR2) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS3 
Attribute R/W  R/W 
Initial value 0b0000000  0 
Note:  This register is placed above the STC register. 
[bit 15:9] res: Reserved bits  The read value is 0. 
Set 0 to this bit. 
 
[bit 8] CKS3: Count clock selection bit  See Count clock selection bit in  9.4.2 Timer Control Register (High-order bytes of TMCR). 
FUJITSU SEMICO NDUCTOR LIMITED 
CHAPTER  14-2: Base...

 
9. Descriptions of base timer functions 
 
 Status Control Register (STC) 
 
bit 7 6 5 4 3 2 1 0 
Field ERR EDIE res OVIE res EDIR res OVIR 
Attribute  R R/W R/W  R/W R/W  R R/W R/W 
Initial value  0 0 0  0 0 0 0 0 
Note:  The TMCR2 register is placed in the upper bytes of this register. 
[bit 7] ERR: Error flag bit    This flag indicates that the next measurement has been completed in continuous measurement mode 
before the measurement result is read from the DTBF  register. In this case, the result...

 
9. Descriptions of base timer functions 
 
[bit 2] EDIR: Measurement completion interrupt request bit 
   This bit indicates that the completion of measurement.  The flag is set to 1 when the measurement is 
completed. 
   The EDIR bit is cleared by read ing the measurement result (DTBF). 
   The EDIR is read-only. Writing a value does not affect the bit value. 
Bit Description 
0  Reads the measurement result (DTBF). 
1  Detects an interrupt cause. 
 
[bit 1] res: Reserved bit  The read value is 0....

 
9. Descriptions of base timer functions 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Base Timer 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  80 
9.4.3. Data Buffer Register (DTBF) 
The Data Buffer Register (DTBF) is a register  that reads the measured or count value of the 
PWC timer. In 32-bit mode, the value of the lower 16 bits is read for the even channel and that 
of the upper 16 bits for the odd channel. 
Be sure to use the 16-bit data transfer instruction to read this register. 
 
bit 15       0 
Field...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
494 
MB9Axxx/MB9Bxxx  Series