Fujitsu Series 3 Manual

 
9. Descriptions of base timer functions 
 
9.1.5. PWM timer operation flowchart 
This section provides an operation flowchart of the PWM timer. 
 PWM timer operation flowchart 
 
PWM mode selection
Count clock selection
Operation mode selection
Interrupt flag clear
Interrupt enableSettings
Start by the CTEN bit
One-shot operation
Continuous operation
Trigger detection 
 TGIR flag setting
Start of decrement
Occurrence of an underflow 
 UDIR flag setting
MDSE=0 ? No
Match in duty 
 DTIR flag setting...

 
9. Descriptions of base timer functions 
 
9.1.6. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PWM 
timer is selected 
The Timer Control Register (TMCR) controls the PWM timer. Note that some bits cannot be 
rewritten while the PWM timer is in operation. 
 Timer Control Register (H igh-order bytes of TMCR) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS2 CKS1 CKS0 RTGENPMSK EGS1 EGS0 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0...

 
9. Descriptions of base timer functions 
 
[bit 11] RTGEN: Restart enable bit This bit enables restart by a software trigger or trigger input. 
Bit Description 
0 Restart  disabled 
1 Restart  enabled 
 
[bit 10] PMSK: Pulse output mask bit    This bit controls the output level of PWM output waveforms. 
   When this bit is set to 0, PWM waveforms are output as they are. 
   When this bit is set to 1, the PWM output is masked with LOW output regardless of the cycle and duty 
set values. 
 
When...

 
9. Descriptions of base timer functions 
 
 Timer Control Register (L ow-order bytes of TMCR) 
 
bit 7 6 5 4 3 2 1 0 
Field res FMD2 FMD1 FMD0 OSEL  MDSE CTEN STRG 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 6:4] FMD2 to FMD0: Timer function selection bits    These bits select the timer function. 
   When the FMD2, FMD1, and FMD0 bits are set to 0b001, the PWM function is selected. 
...

 
9. Descriptions of base timer functions 
 
[bit 2] MDSE: Mode selection bit   This bit selects continuous pulse output or one-shot pulse output. 
   Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make 
changes at the same time you set 1 to the CTEN bit. 
Bit Description 
0 Continuous  operation 
1 One-shot operation 
 
[bit 1] CTEN: Count operation enable bit    This bit enables the operation of the down counter. 
   When the counter is in operation en abled...

 
9. Descriptions of base timer functions 
 
 Timer Control Register 2 (TMCR2) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS3 
Attribute R/W  R/W 
Initial value 0b0000000  0 
Note:  This register is placed above the STC register. 
 
[bit 15:9] res: Reserved bits  The read value is 0. 
Set 0 to this bit. 
 
[bit 8] CKS3: Count clock selection bit  See Count clock selection bit in  9.1.6 Timer Control Register (TMCR). 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  14-2: Base Timer 
MN706-00002-1v0-E 
440...

 
9. Descriptions of base timer functions 
 
 Status Control Register (STC) 
 
bit 7 6 5 4 3 2 1 0 
Field res TGIE DTIE UDIE  res TGIR DTIR UDIR 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
Note:  The TMCR2 register is placed in the upper bytes of this register. 
 
[bit 7] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 6] TGIE: Trigger interrupt request enable bit    This bit controls interrupt requests of bit 2 TGIR. 
   When the TGIE bit is...

 
9. Descriptions of base timer functions 
 
[bit 2] TGIR: Trigger interrupt request bit   When a software trigger or trigger input is detected, the TGIR bit is set to 1. 
   The TGIR bit is cleared by writing 0. 
   Even if 1 is written to the TGIR  bit, the bit value is not affected. 
   The read value of read-modify-write instructions is 1 regardless of the bit value. 
Bit Description 
0  Clears an interrupt cause. 
1 Detects an interrupt cause. 
 
[bit 1] DTIR: Duty match interrupt request bit  ...

 
9. Descriptions of base timer functions 
 
9.1.7. PWM Cycle Set Register (PCSR) 
The PWM Cycle Set Register (PCSR) is a buffered register for setting the cycle. Transfer to 
the Timer Register is performed at startup and underflow. 
 bit 15       0 
Field PCSR [15:0] 
Attribute R/W 
Initial value  0xXXXX 
 
This is a buffered register for setti ng the cycle. Transfer to the Timer Re gister is performed at startup and 
underflow. 
When initializing or rewriting the PWM Cycle Set Regist er, be sure to...

 
9. Descriptions of base timer functions 
 
9.1.8. PWM Duty Set Register (PDUT) 
The PWM Duty Set Register (PDUT) is a buffered register for setting the duty. Transfer from 
the buffer is performed at an underflow. 
 bit 15       0 
Field PDUT [15:0] 
Attribute R/W 
Initial value  0xXXXX 
 
This is a buffered register for setting the duty. Transfer from the buffer is performed at an underflow. 
When the cycle set register value is set equal to the du ty set register value, an all-HIGH pulse is output...