Fujitsu Series 3 Manual
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Page 441
3. I/O Mode I/O mode 7 (Timer start mode) This mode uses the output waveform from the even channel (TOUT signal) as input signals (ECK/TGIN/TIN signals) of the odd channel. Table 3-23 shows the external pins used when this mode is selected. Table 3-23 External pins used when I/O mode 7 is selected. Even channel Odd channel Number of input pins 1 Not used Number of output pins 1 1 Table 3-24 shows the internal signals to which the external pins connect, and signals input or output....
Page 442
3. I/O Mode I/O mode 8 (Shared channel signal trigger and timer start/stop mode) This mode inputs the COUT signal from channels below the two channels as a CIN signal, and uses it as an external startup trigger (TGIN signal). Table 3-26 shows the external pins used when this mode is selected. Table 3-26 External pins used when I/O mode 8 is selected. Even channel Odd channel Number of input pins Not used Number of output pins 1 1 Table 3-27 shows the internal signals to which the...
Page 443
3. I/O Mode The following shows Ch.n-2/n-1 signals that can be input to ECK/TGIN/TIN of Ch.n/n+1. Signal that the peripheral clock generates by synchronizing TIOBn-2 input in I/O mode 2. Trigger signal input from Ch.n-4/n-3 in I/O mode 3. TIOAn-2 output in I/O mode 4. TIOAn-2 output in I/O mode 6. TIOAn-2 output in I/O mode 7. Trigger signal input from Ch.n-4/n-3 in I/O mode 8. The ch a nnels set to this mode use the COUT signal from lower 2 channels (n-2 and...
Page 444
4. Registers 4. Registers This section provides the register list of the base timer I/O select function. Base Timer I/O Select Function Registers Table 4-1 Base timer I/O select function register list Abbreviation Register name See BTSEL0123 I/O Select Register 4.1 BTSEL4567 I/O Select Register 4.2 BTSSSR Software-based Simultaneous Startup Register 4.3 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 408 MB9Axxx/MB9Bxxx Series
Page 445
4. Registers 4.1. I/O Select Register (BTSEL0123) This register selects the I/O mode for channels 0 to 3 of the base timer. Register configuration bit 15 14 13 12 11 10 9 8 Field SEL23_3SEL23_2 SEL23_1 SEL23_0SEL01_3SEL01_2 SEL01_1 SEL01_0 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Register functions [bit 15:12] SEL23_3 to SEL23_0: I/O select bits for Ch.2/Ch.3 Bit 15 Bit 14 Bit 13 Bit 12 I/O select bit 0 0 0 0 I/O mode 0 (Standard 16-bit...
Page 446
4. Registers [bit 11:8] SEL01_3 to SEL01_0: I/O select bits for Ch.0/Ch.1 Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit 0 0 0 0 I/O mode 0 (Standard 16-bit timer mode) 0 0 0 1 I/O mode 1 (Timer full mode) 0 0 1 0 I/O mode 2 (Shared external trigger mode) 0 0 1 1 I/O mode 3 (Shared channel signal trigger mode) 0 1 0 0 I/O mode 4 (Timer start/stop mode) 0 1 0 1 I/O mode 5 (Software-based simultaneous startup mode) 0 1 1 0 I/O mode 6 (Software-based startup an d timer...
Page 447
4. Registers 4.2. I/O Select Register (BTSEL4567) This register selects the I/O mode for channels 4 to 7 of the base timer. Register configuration bit 15 14 13 12 11 10 9 8 Field SEL67_3SEL67_2 SEL67_1 SEL67_0SEL45_3SEL45_2 SEL45_1 SEL45_0 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Register functions [bit 15:12] SEL67_3 to SEL67_0: I/O select bits for Ch.6/Ch.7 Bit 15 Bit 14 Bit 13 Bit 12 I/O select bit 0 0 0 0 I/O mode 0 (Standard 16-bit...
Page 448
4. Registers [bit 11:8] SEL45_3 to SEL45_0: I/O select bits for Ch.4/Ch.5 Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit 0 0 0 0 I/O mode 0 (Standard 16-bit timer mode) 0 0 0 1 I/O mode 1 (Timer full mode) 0 0 1 0 I/O mode 2 (Shared external trigger mode) 0 0 1 1 I/O mode 3 (Shared channel signal trigger mode) 0 1 0 0 I/O mode 4 (Timer start/stop mode) 0 1 0 1 I/O mode 5 (Software-based simultaneous startup mode) 0 1 1 0 I/O mode 6 (Software-based startup an d timer start/stop mode) 0 1...
Page 449
4. Registers FUJITSU SEMICONDUCTOR LIMITED Chapter: Base Timer I/O Select Function FUJITSU SEMICONDUCTOR CONFIDENTIAL 28 4.3. Software-based Simultaneous Startup Register (BTSSSR) This register starts up multiple base timer channels using software. Up to 16 channels can be started simultaneously if the bits corresponding to the channel are set to 1. Register configuration bit 15 - 0 Field SSSR15 to 0 Attribute W Initial value X Register functions [bit 15:0] SSSR15 to...
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