Fujitsu Series 3 Manual

 
1. Overview of the Watch Counter 
 
CHAPTER: Watch Counter 
This chapter explains the functions and operations of the watch counter. 
 
1.
 Overview of the Watch Counter 
2. Configuration of the Watch Counter 
3. Interrupts of the Watch Counter 
4. Explanation of Operations and Setting Pr ocedure Examples of the Watch Counter 
5. Registers of the Watch Counter 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFWC-E01.2_FW09-J00.4 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  13-2: Watch  Counter...

 
1. Overview of the Watch Counter 
 
1.  Overview of the Watch Counter 
The watch counter is a timer that counts down starting from the specified value, and it 
generates an interrupt request at the time that the 6-bit down counter enters an underflow 
condition. 
  Watch counter 
  For the watch counter, one of the four types of clock (WCCK0, WCCK1, WCCK2, and WCCK3) 
selected by the CS1 and CS0 bits of the watch counter control register (WCCR) is used as a count clock 
of the 6-bit down counter. 
...

 
2. Configuration of the Watch Counter 
 
2.  Configuration of the Watch Counter 
This section shows the watch counter block diagram. 
  Block diagram of the watch counter 
Figure 2-1  shows a block diagram of the watch counter. 
Figure 2-1 Block diagram of the watch counter 
 
Internal bus 
WCIF
WCIE
CS0 
CS1 
WCOP 
WCEN  Count 
clock selection 
6-bit 
down counter 
Underflow 
Interrupt request 
Counter clearing 
RLC5 RLC4  RLC3 RLC2 RLC1 RLC0
CTR5 CTR4 CTR3 CTR2 CTR1 CTR0
Counter value 
Reload value...

 
3. Interrupts of the Watch Counter 
 
3.  Interrupts of the Watch Counter 
The 6-bit down counter enters an underflow condition when the value in the 6-bit down 
counter becomes 0b000001, and an underflow interrupt request is then generated. 
  Interrupts of the watch counter 
Ta b l e  3 - 1  outlines the interrupts that can be used with the watch counter. 
Table 3-1 Interrupts of the watch counter 
Interrupt request  Interrupt request 
flag  Interrupt request 
enabled  Clearing an interrupt 
request...

 FUJITSU SEMICONDUCTOR LIMITED 
4.  Explanation of Operations and Setting Procedure Examples of the Watch Counter 
This section explains operations of the watch counter. Also, examples of procedures for 
setting the operating state are shown. 
 Setting procedure examples of the watch counter 
To operate the watch counter, follow the procedure below. 
(1)  Select a count clock by using the CS1 and CS0 bits of the watch counter control register (WCCR). 
(2)  Set a count value to the RLC5 to RLC0 bits  in...

 FUJITSU SEMICONDUCTOR LIMITED 
Figure 4-1 shows the operation of the watch counter. 
Figure 4-1 Operation explanation figure of the watch counter 
 WCEN bit
Count clock
CS1 and CS0 bits(1) 
RLC5 to RLC0 bits
CTR5 to CTR0 bits WCIF bit
0 7 65432198765 4 
7 9 
(4) (6)
(5)
(3) (7) 
(2)  
 
    The peri phe

ral clock (PCLK) is used for the settings of each register of the watch counter. Since the 
count cl oc

k and peripheral clock (PCLK) are not synchronized, an error of up to 1T (T: Count clock...

 
5. Registers of the Watch Counter 
 
5.  Registers of the Watch Counter 
This section explains the registers for the watch counter. 
  List of the registers for the watch counter 
Table 5-1 List of registers for the watch counter 
Abbreviated 
Register Name  Register Name See 
WCRD 
Watch counter read register  5.1 
WCRL Watch counter reload register  5.2 
WCCR Watch counter control register  5.3 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  13-2: Watch  Counter 
MN706-00002-1v0-E 
381 
MB9Axxx/MB9Bxxx...

 
5. Registers of the Watch Counter 
 
5.1.  Watch Counter Read Register (WCRD) 
This register reads the value in the 6-bit down counter. 
 
bit 7 6 5 4 3 2 1 0 
Field res CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 
Attribute  R R R R  R R R 
Initial value 0b00 0 0 0  0 0 0 
 
[bit7:6] res : Reserved bits  0 is always read. 
Writing is ignored. 
 
[bit5:0] CTR5 to CTR0 : Counter read bits  These bits can read the counter value. 
Writing is ignored. 
 
 
If the 

6-bit down counter is operating when its value is...

 
5. Registers of the Watch Counter 
 
5.2.  Watch Counter Reload Register (WCRL) 
This register specifies the value used by the watch counter to start counting. The 6-bit down 
counter counts down starting from the value set in the register. 
The register specifies the reload va lue for the 6-bit down counter. If the 6-bit down counter enters an 
underflow condition, the value in this register is re loaded in the 6-bit down counter, and the countdown is 
restarted. 
 
bit 15 14 13 12 11 10 9 8 
Field...

 
5. Registers of the Watch Counter 
 
5.3.  Watch Counter Control Register (WCCR) 
This register selects a count clock for the watch counter or enables/disables generation of 
interrupt requests. The register also enables/disables the operation of the watch counter. 
 
bit 23 22 21 20 19 18 17 16 
Field WCEN WCOP res  CS1 CS0 WCIE WCIF 
Attribute R/W R  R R/W R/W  R/W R/W 
Initial value 0 0  0b00 0 0  0 0 
 
[bit23] WCEN : Watch counter operation enable bit  This bit enables the operation of the watch...