Fujitsu Series 3 Manual

 
6. Registers 
 
6.4.  Software Watchdog Timer Clear Register (WdogIntClr) 
WdogIntClr register clears the software watchdog timer. 
 Register configuration 
bit  31         0 
Field WdogIntClr 
Attribute R/W 
Initial value  0xxxxxxxxx 
 
  Register function 
[bit31:0] WdogIntClr : clear bit 
bit31:0 Explanation 
In case of reading  An undefined bit is read. 
In case of writing Writing an arbitrary value 

  Clears an interrupt of the watchdog timer, if an interrupt of the watchdog 
timer is...

 
6. Registers 
 
6.5.  Software Watchdog Timer Interrupt Status Register (WdogRIS) 
WdogRIS register shows the status of the software watchdog timer. 
 Register configuration 
bit  7       1 0 
Field Reserved  RIS 
Attribute -  R 
Initial value - 1’b0 
 
  Register function 
[bit7:1] res : Reserved bits 
0b0000000 is read from these registers. 
In case of writing, set 0b0000000. 
[bit0] RIS : Software watchdog interrupt status bit 
bit Explanation 
In case of writing  No effect. 
In case of reading 0...

 
6. Registers 
 
6.6.  Software Watchdog Timer Lock Register (WdogLock) 
WdogLock register controls accesses of all the registers of software watchdog timer. 
 Register configuration 
bit  31         0 
Field WdogLock 
Attribute R/W 
Initial value  0x00000000 
 
  Register function 
[bit31:0] WdogLock : Software watchdog lock register 
bit31:0 Explanation 
In case of writing  Writing 0x1ACCE551: 
    Releases locks of all the registers of software watchdog timer. 
Writing other than 0x1ACCE551:...

 
6. Registers 
 
6.7.  Hardware Watchdog Timer Load Register (WDG_LDR) 
WDG_LDR register sets the cycle of hardware watchdog timer. 
 Register configuration 
bit  31         0 
Field WDG_LDR 
Attribute R/W 
Initial value  0x0000FFFF 
 
  Register function 
[bit31:0] WDG_LDR : Interval cycle setting bit 
bit31:0 Explanation 
In case of writing  Sets cycle of the hardware watchdog. 
The initial value is 0x0000FFFF. 
The minimum value of writing is 1. 
An interrupt is generated after 0 is written. 
In...

 
6. Registers 
 
6.8.  Hardware Watchdog Timer Value Register (WDG_VLR) 
WDG_VLR register can read the current counter value of the hardware watchdog timer. 
 Register configuration 
bit  31         0 
Field WDG_VLR 
Attribute R 
Initial value  0xxxxxxxx 
 
  Register function 
[bit31:0] WDG_VLR : Counter value bit 
bit31:0 Explanation 
In case of reading  The current count value of the watchdog counter can be read. 
By turning on the power, the hardware watchdog automatically activates, 
therefore...

 
6. Registers 
 
6.9.  Hardware Watchdog Timer Control Register (WDG_CTL) 
WDG_CTL register sets enable/disable of the hardware watchdog timer. 
 Register configuration 
bit  7      2 1  0 
Field Reserved  RESEN INTEN
Attribute -  R/W R/W 
Initial value  - 1’b1 1’b1 
 
  Register function 
[bit7:2] res : Reserved bits 
0b000000 is read from these bits. 
In case of writing, set these bits to 0b000000. 
[bit1] RESEN : Hardware wa tchdog timer reset enable bit 
bit Explanation 
In case of reading  A...

 
6. Registers 
 
6.10.  Hardware Watchdog Timer Clear Register (WDG_ICL) 
WDG_ICL register clears the hardware watchdog timer. 
 Register configuration 
bit  7         0 
Field WDG_ICL 
Attribute R/W 
Initial value  0xxx 
 
  Register function 
[bit7:0] WDG_ICL : clear bit 
bit7:0 Explanation 
In case of reading  Undefined value is read. 
In case of writing Writing an arbitrary 8-bit value, and then write a reversal value of the 
arbitrary value, 

  Clears an interrupt, if an interrupt of watchdog...

 
6. Registers 
 
6.11.  Hardware Watchdog Timer Interrupt Status Register (WDG_RIS) 
WDG_RIS register shows the status of the hardware watchdog timer. 
 Register configuration 
bit  7       1 0 
Field Reserved  RIS 
Attribute -  R 
Initial value - 1’b0 
 
  Register function 
[bit7:1] res : Reserved bits 
0b0000000 is read from these bits. 
In case of writing, set 0b0000000. 
[bit0] RIS : Hardware watchdog interrupt status bit 
bit Explanation 
In case of writing  No effect 
In case of reading 0...

 
6. Registers 
 
6.12.  Hardware Watchdog Timer Lock Register (WDG_LCK) 
WDG_LCK register controls all the registers of the hardware watchdog timer. 
 Register configuration 
bit  31         0 
Field WDG_LCK 
Attribute    R/W    
Initial value     0x00000001    
 
  Register function 
[bit31:0] WDG_LCK : Hardware watchdog lock register 
bit31:0 Explanation 
In case of writing  In case of writing 0x1ACCE551: 
    The locks of all the registers other than the control register are released.
Later, in...

 
7. Notes 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Watchdog timer 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  30  
7. Notes 
The section explains the notes when using the watchdog timer. 
  Hardware watchdog timer clear register 
To clear the hardware watchdog, write an arbitrary 8- bit value, and then write a reversal value of the 
arbitrary value. Clearing cannot be performed unles s the correct reversal value is written. Even if 
clearing is not performed, the  register is locked again. 
   Cooperation...