Fujitsu Series 3 Manual

 
7. Usage Precautions 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Clock supervisor 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  20 
7. Usage Precautions 
This section explains the precautions for using clock supervisor functions. 
   For details on enabling and clearing the frequency  detection interrupt sources, see Chapter Clocks. 
 
   For details on clock failure detection and anomalous frequency detection reset sources, see Chapter 
Resets. 
 
   Operation after the occurrence of a reset. 
After the...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
316 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
CHAPTER: Watchdog timer 
This chapter describes the watchdog timer. 
 1.
 Overview 
2. Configuration and Block Diagram 
3. Operations 
4. Setting Procedure Example 
5. Operation Example 
6. Registers 
7. Notes 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFWDT-E02.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  11: Watchdog  timer 
MN706-00002-1v0-E 
317 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
This section describes the overview of the watchdog timer. 
The watchdog timer is a function to detect runaway of user program. 
If the watchdog timer is not cleared within the specified interval time, it judges that a user program is out of 
control, and outputs a system reset request or an interrupt request to CPU. 
This interrupt is called a watchdog in terrupt request, and a reset request is called a watchdog reset request. 
During watchdog timer operation, it is...

 
2. Configuration and Block Diagram 
 
2.  Configuration and Block Diagram 
This section shows the configuration and block diagram of the watchdog timer. 
Figure 2-1 Block Diagram of Software Watchdog Timer 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
APB 
bus SWDG 
reset 
SWDG 
interrupt 
TOOL break signal
 
Software Watchdog Timer 
System reset 
APB 
interface  
32bit down counter  
Control register
Lock register 
Value register 
Load register 
Interrupt/ 
reset 
generation 
circuit 
Control logic/register...

 
2. Configuration and Block Diagram 
 
Figure 2-2 Block Diagram of Hardware Watchdog Timer 
 
FUJITSU SEMICONDUCTOR LIMITED 
  
 Control register 
Hardware Watchdog Timer 
APB 
interface 
32bit down counter 
Control register 
Lock register 
Value register 
Load register 
Interrupt/ 
reset 
generation 
circuit 
Control logic/register 
System reset 
TOOL break signal  
HWDG clock 
Clear register 
APB 
bus HWDG 
interruptHWDG 
reset 
CHAPTER  11: Watchdog  timer 
MN706-00002-1v0-E 
320 
MB9Axxx/MB9Bxxx...

 
3. Operations 
 
3. Operations 
This section shows the operation of watchdog timer. 
The watchdog timer consists of the following blocks. 
 Software Watchdog Timer 
  Control register / logic 
This circuit controls the software watchdog timer. 
It consists of the load register, the lock regi ster, the control register, and the clear register. 
   Load register (WdogLoad) 
This register is a 32-bit register used to set count interval cycles of the software watchdog timer. The 
initial value is...

 
3. Operations 
 
 Watchdog Timer Counter (32-bit Down Counter) 
This is a 32-bit down counter. The count value is re loaded from the set value of the load register 
(WdogLoad) by accessing  to the clear register (WdogIntClr) before the coun ter value becomes 0 by 
decrementing. 
Ta b l e  3 - 2  shows the down counter reload condition. 
Table 3-2 Down Counter Reload Condition of Software Watchdog Timer 
Reload Conditions 
Accessing to the clear register (WdogIntClr) 
When the down counter reaches 0...

 
3. Operations 
 
 Halting the software watchdog timer 
  The software watchdog timer is stopped by accessing  to the control register (WdogControl), and writing 
0 to the watchdog interrupt enable bit. 
   The software watchdog timer is stopped by generating a reset. 
 Hardware Watchdog Timer 
  Control register / logic 
This is a circuit to control the hardware watchdog timer. 
It consists of the load register, the lock regi ster, the control register, and the clear register. 
   Load register...

 
3. Operations 
 
 Interrupt and reset generation circuit 
When an underflow of the watchdog timer counter is detected, a watchdog interrupt and a watchdog reset 
are generated due to the register setting. 
  Interrupt status register (WDG_RIS) 
This register shows the status of a hardware watchdog interrupt. 
  Activation of hardware watchdog timer 
  Writing 0x1ACCE551 to the lock register (WDG_LCK) and then writing a reversal value 
0xE5331AAE to it enables to access to the control register...