Fujitsu Series 3 Manual

 
5. Usage Precautions 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: I/O PORT 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  65 
  Rreserved Bit 
This bit is read out as 0 except for the ADE rese rved bit. When writing, always write 0. The ADE 
reserved bit is read out as 1.  When writing, always write 1. 
 Connecting External Bus Pin and SRAM 
When accessing SRAM via external bus, either perform pull-up setting for the pin or connect it to external 
pull-up pin. 
  Multi-function Serial Pin Group 
When there are...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
296 
MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
Chapter: Clock supervisor 
This chapter explains clock supervisor functions. 
 
1.
 Overview 
2. Configurations and Block Diagrams 
3. Explanation of Operations 
4. Setup Procedure Examples 
5. Operation Examples 
6. Register list 
7. Usage Precautions 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFCSV-E02.1 
CHAPTER  10: Clock  supervisor 
MN706-00002-1v0-E 
297 
MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
1. Overview 
This section provides an overview of clock supervisor functions. 
The clock supervisor includes the following two types of functions. 
 Clock failure detection (CSV: Clock failu re detection by clock Super Visor) 
The clock failure detection monitors the main and sub clocks. If a rising edge of the monitored clock is not 
detected within the specified period, this function determines that the oscillator has failed, and outputs a 
system reset request. 
...

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2.  Configurations and Block Diagrams 
This section explains the block diagrams of clock supervisor functions. 
 Clock failure detection 
Figure 2-1  shows the block diagram of the clock failure detection. 
Figure 2-1 Clock Failure Detection Block Diagram 
 
Main clock 
counter
Control circuit/ registers
Sub clock counter
Main OSC
Sub OSC
Low-speed CR CSV_RESET
High-speed CR
  
 
The clock failure detection consists of the following three types of blocks. 
 Control...

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 Anomalous frequency detection 
Figure 2-2  shows the block diagram of the anomalous frequency detection. 
Figure 2-2 Anomalous Frequency Detection Block Diagram 
 
Frequency 
counter
Control circuit/registers and 
window registers
Edge 
detectiondivider
FCS_RESET
FCS_INT
Main OSC
High-speed CR
  
  The anomalous frequency detection consists of the following three types of blocks. 
 Control circuit/register s and window registers 
  This block includes a circuit...

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3.  Explanation of Operations 
This section explains the operations of clock supervisor functions. 
 Clock failure detection 
The clock failure detection monitors the main and sub clocks. If a rising edge of the monitored clock is not 
detected within the specified period, this function determines that the oscillator has failed, and outputs a 
system reset request. 
  This reset request is referred to as the CSV reset request. 
   CSV function monitors each of the main...

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4.  Setup Procedure Examples 
This section explains examples of setting up clock supervisor functions. 
 Example clock failure detection setup procedure 
 
  
Stop Monitoring? 
Oscillation stabilization wait time of 
main and sub clocks end
No 
Ye s
No
End 
Access the CSV_CTL register 
Disable the enable bit 
Clock failure detection function  enables 
Failure Detected? 
Ye s  
The CSV reset occurs 
Enable main and sub clock oscillators 
Start 
 
CHAPTER  10: Clock...

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 Example frequency detection setup procedure 
 
 
Start 
 
 
Access CSV_CTL 
Enable/disable the FCS reset 
Access FCSWL_CTL 
Set lower frequency window 
Access INT_CLR 
Clear the FCS interrupt source 
End 
Access CSV_CTL 
Set FCD (Count Edge setting) 
Access FCSWH_CTL 
Set upper frequency window Is the count value out of the window? No
Ye s
Ye s 
Is the interrupt flag set? 
FCS interrupt occurs 
Restart interrupt handling/FCS function 
No
The FCS reset occurs 
Is the FCS...

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5. Operation Examples 
This section explains examples of clock supervisor operations. 
 Clock failure detection 
Figure 5-1  provides an example of cloc k failure detect ion operation. 
Figure 5-1 Example clock failure detection operation 
Main clock
High-speed  CR clock
Main clock is missing
32 x CR clocks
CSV reset
Reset occurs
 
1. The main clock stops due to failure. 
2.  The function counts up clocks using the high-speed CR clock. 
3.  If the main clock keeps stopping...