Fujitsu Series 3 Manual

 
3. Operations 
 
 Differences between software watchdog  timer and hardware watchdog timer 
Ta b l e  3 - 6 shows the major differences between software  watchdog timer an d hardware watchdog timer. 
Table 3-6 Differences between software watchdog timer and hardware watchdog timer 
 Software Watchdog Hardware Watchdog 
Count clock  Divided clock of APB  CLKLC 
Read value of the value 
register Synchronous reading 
Reading possible  Asynchronous reading 
Only during tool break, a correct value 
can be...

 
4. Setting Procedure Example 
 
4.  Setting Procedure Example 
This section explains a setting procedure example of watchdog timer. 
 Software watchdog timer 
Figure 4-1 Setting procedure example of software watchdog timer 
 
Start setting 
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Write interval time to load register 
(WdogLoad) 
Write 0x1ACCE551 to WdogLock
Access to control register (WdogControl)
interrupt and reset enable 
Access WdogIntClr and clear watchdo
g counter 
Write WdogLock with a value other...

 
4. Setting Procedure Example 
 
 Hardware watchdog timer 
Figure 4-2 Setting procedure example of hardware watchdog timer 
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Activate hardware watchdog timer 
 
 
INTEN=0 
Write interval time to load register 
(WDG_LDR) 
Write 0x1ACCE551 to WDG_LCK 
Access to control register (WDG_CTL)
set interrupt and reset enable 
Access WDG_ICL and write  arbitrary value 
Automatically lock registers again 
Watch ow ? 
dog counter underfl
Interrupt flag=1 ? 
Watchdog reset is...

 
5. Operation Example 
 
5. Operation Example 
This section shows an operation example of the watchdog timers. 
 Software watchdog timer 
Figure 5-1 Operation example of software watchdog timer 
 
  
Watchdog 
counter value 
Initial value 
0xFFFFFFFF Operation halts  Operation halts 
Set value example 
0x111FFFFF 
Set value example 0x0000FFFF 
Time
1. Interval setting 
0x111FFFF3. Watchdog 
counter clear7. Transit 
to STOP  mode 
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1.  Set SWC_PSR, WDGT_CTL before...

 
5. Operation Example 
 
9. A software watchdog reset will be generated when the second underflow is generated without clearing 
the interrupt WdogIntClr register. 
The software watchdog timer stops its operation by generating a reset. 
 
Release of the lock re gister is 

required to access each register. It is omitted in the  ope
 ration example. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  11: Watchdog  timer 
MN706-00002-1v0-E 
329 
MB9Axxx/MB9Bxxx  Series  

 
5. Operation Example 
 
 Hardware watchdog timer 
Figure 5-2 Operation example of hardware watchdog timer 
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Watchdog 
counter value 
Set value example 
0xFFFFFFFF 
Initial value 
0x0000FFFF 
Time 
3. Watchdog 
counter clea
r1. t 
af  Operation star
ter 
power-o5.  P 
Release STO
mode
n 
7. Underflow 
reset generated 
4. Transit to 
STOP mode2. Interval setting  0xFFFFFFFF 6. Underflow 
interrupt generated 
1.  Hardware watchdog timer starts operation after turning on...

 
6. Registers 
 
6. Registers 
This section explains the registers of clock generation. 
Table 6-1 List of registers for the watchdog timer Register Name Explanation Reference
WdogLoad Software watchdog timer load register  6.1 
WdogValue Software watchdog timer value register  6.2 
WdogControl Software watchdog timer control register  6.3 
WdogIntClr Software watchdog timer clear register  6.4 
WdogRIS Software watchdog timer  interrupt status register  6.5 
WdogLock Software watchdog timer lock...

 
6. Registers 
 
6.1.  Software Watchdog Timer Load Register (WdogLoad) 
WdogLoad register sets the cycle of the software watchdog timer. 
 Register configuration 
bit  31         0 
Field WdogLoad 
Attribute R/W 
Initial value  0xFFFFFFFF 
 
  Register function 
[bit31:0] WdogLoad : Interval cycle setting bit 
bit31:0 Explanation 
In case of writing  Sets the cycle of the software watchdog. 
The initial value is 0xFFFFFFFF. 
 
The minimum value for writing is 1. 
When 0 is written, an interrupt will...

 
6. Registers 
 
6.2.  Software Watchdog Timer Value Register (WdogValue) 
WdogValue register can read the current value of the software watchdog timer. 
 Register configuration 
bit  31        0 
Field WdogValue 
Attribute R 
Initial value  0xFFFFFFFF 
 
  Register function 
[bit31:0] WdogValue : Counter value bit 
bit31:0 Explanation 
In case of writing  No effect. 
In case of reading  The count value of the current watchdog counter is read. 
The initial value 0xFFFFFFFF is re
ad if reading before...

 
6. Registers 
 
6.3.  Software Watchdog Timer Control Register (WdogControl) 
WdogControl register sets enable/disable of the software watchdog timer. 
 Register configuration 
bit  7      2  1  0 
Field Reserved  RESEN INTEN
Attribute -  R/W R/W 
Initial value  - 1’b0 1’b0 
 
  Register function 
[bit7:2] res : Reserved bits 
0b000000 is read from these bits. 
In case of writing, set 0b000000. 
[bit1] RESEN : Reset enable bit of the software watchdog 
bit Explanation 
In case of reading  Register...