Fujitsu Series 3 Manual

 
5. Register 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Dual Timer 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  22  
5.7.  Background Load Register (TimerXBGLoad)   
X=1 or 2 
Background Load Register (TimerXBGLoad) is a  32-bit register having a value which the 
counter starts to decrement.   
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXBGLoad[31:16] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
bit 15 14 13 12 11 109 8...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
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MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Watch Counter Prescaler 
This chapter explains the functions and operations of the watch counter prescaler. 
 1.
 Overview of the Watch Counter Prescaler 
2. Configuration of the Watch Counter Prescaler 
3. Explanation of Operations an d Setting Procedure Examples of  the Watch Counter Prescaler 
4. Registers of the Watch Counter Prescaler 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFWCPRE-E01.1 
CHAPTER  13-1: Watch  Counter  Prescaler...

FUJITSU SEMICONDUCTOR LIMITED 
1.  Overview of the Watch Counter Prescaler 
The watch counter prescaler is a prescaler which generates a counter clock used for a watch 
counter. 
 Watch Counter Prescaler 
This is a prescaler which generates  a count clock of the watch counter. 
The watch counter prescaler can select a main  clock or a sub clock as an input clock (F
CL). The watch 
counter prescaler outputs the division clocks (WCCK0 to 3) shown in  Table 1-1 by setting SEL_OUT bit of 
the clock sel e...

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2.  Configuration of the Watch Counter Prescaler 
This section shows the block diagram of the watch counter prescaler. 
 Block diagram of the  watch counter prescaler 
Figure 2-1 shows the block diagram of the watch counter prescaler. 
Figure 2-1 Block diagram of the watch counter prescaler 
 
Internal bus 
Division counter 
(down counter) 
FCL : Frequency of input clock  SEL_IN 
CLK_EN Count enabled
SEL_OUT 
Main clock 
Sub clock 
FCL  WCCK0 
WCCK1 
WCCK2 
WCCK3 
Input...

 FUJITSU SEMICONDUCTOR LIMITED 
3.  Explanation of Operations and Setting Procedure Examples of the Watch Counter Prescaler 
This section explains the operations of the watch counter prescaler. Also, procedures for 
setting the operating state are shown. 
 Procedures for setting the watch counter prescaler 
The procedures for setting the watch  counter prescaler are shown below. 
 To start output of the division clock 
1.  Select the input clock (FCL) of the division counter with SEL_IN bit of the...

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 Operation of the watch counter prescaler 
Figure 3-1  shows an operation of the watc h counter prescaler when SEL_ OUT is set to 0 as an example. 
Figure 3-1 Operation explanation diagram of the watch counter prescaler 
 
CLK_EN bit
Input clock F
CL 
Division counter
WCCK0
WCCK2
WCCK3
WCCK1
Peripheral clock
 (PCLK)
0 0x1FF FFFF 
(1) 
(2)
(3)0x1FF FFFE  0x1FF 
DFFE 0x1FF F7FE0x1FFEFFE0x1FF BFFE 0x1FF
7FFE
  
 
(1) Set CLK_EN bit at rising of the peripheral clock (PCLK)....

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4.  Registers of the Watch Counter Prescaler 
This section explains the registers for the watch counter prescaler. 
 List of registers for th e watch counter prescaler 
Table 4-1 List of registers for the watch counter prescaler 
Abbreviated 
Register Name  Register Name Reference 
CLK_SEL Clock selection register 
4.1 
CLK_EN Division clock enable register  4.2 
 
CHAPTER  13-1: Watch  Counter  Prescaler 
MN706-00002-1v0-E 
372 
MB9Axxx/MB9Bxxx  Series  

FUJITSU SEMICONDUCTOR LIMITED 
4.1.  Clock Selection Register (CLK_SEL) 
The clock selection register (CLK_SEL) selects the input clock (FCL) and sets the division 
clocks (WCCK0 to 3) to be output. 
 bit 15 to 11 10 9 8 
Field res res SEL_OUT
Attribute R/W  R/W R/W 
Initial value  0b00000  0b00 0 
  bit 7  to 1 0 
Field res  SEL_IN
Attribute R/W  R/W 
Initial value 0b0000000  0 
 
[bit15:11, bit7:1] res : Reserved bits  0 is always read. 
Writing is ignored. 
 
[bit10: 9] res : Reserved bits  Always...

 
4. Registers of the Watch Counter Prescaler 
 
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CHAPTER: Watch Counter Prescaler 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  9 
4.2.  Division Clock Enable Register (CLK_EN) 
The division clock enable register (CLK_EN) is a register to enable a count down of the 
division counter. 
  bit 7 to 2 1 0 
Field res CLK_EN_R CLK_EN
Attribute R/W  R/W R/W 
Initial value  0b000000  0 0 
 
[bit7:2] res : Reserved bits  0 is always read. 
Writing is ignored. 
 
[bit1] CLK_EN_R : Division...