Fujitsu Series 3 Manual

 
1. Overview 
 
CHAPTER: Dual Timer 
This chapter introduces the Dual Timer functions and operations. 
 
1.
 Overview 
2. Architecture 
3. Operation Description 
4. Setting Procedure Example 
5. Register 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFDT-E01.1_SP804-E01.0 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  12: Dual  Timer 
MN706-00002-1v0-E 
345 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
Dual Timer consists of two programmable 32/16-bit down counters. An interrupt is generated 
when the count reaches zero.   
 Dual Timer Overview 
Dual Timer consists of two programmable Free Running  Counters. Each timer block operates identically. 
The Free Running Counters can be programmed for 32-bit or 16-bit counter size by Control Register. Also, 
any one of the following three  timer modes can be selected: 
   Free-running mode 
The counter operates continuously...

 
2. Architecture 
 
2. Architecture 
This chapter illustrates the Dual Timer architecture.   
Figure 2-1 Dual Timer Block Diagram 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
 
Prescaler Timer1Load Register 
Timer1BGLoad  Register Timer1Control Register 
32/16-bit Down Counter 
Timer1Value Register Interrupt and 
Reload Control 
Interrupt Status Register 
Masked Interrupt Status Register 
Interrupt Clear Register
 
Timer1 Free Running Counter 
APB Interface APB Bus 
Timer1
 Interrupt 
Request 
Time r

 Clock...

 
3. Operation Description 
 
3. Operation Description 
This chapter describes Dual Timer operations. 
 
3.1 Timer Operating Mode 
3.2  Default 
3.3  Interrupt Behavior 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  12: Dual  Timer 
MN706-00002-1v0-E 
348 
MB9Axxx/MB9Bxxx  Series  

 
3. Operation Description 
 
3.1.  Timer Operating Mode 
Operating modes are selected from three timer modes based on the settings of the Control 
Register (TimerXControl)’s mode bit (TimerMode) and one-shot mode bit (OneShot). 
Table 3-1 Mode Selection Table 
TimerMode OneShot Selective Mode 
0 0  Free-running Mode 
1 0  Periodic Mode 
- 1  One-shot Mode 
 
Timer size bit (TimerSize) of the Control Register is us ed to appropriately configure 32-bit or 16-bit counter 
operation.  
 
 
The ch aracter X...

 
3. Operation Description 
 
 Free-running Mode 
When a reset is performed, the timer value is initialized to 0xFFFFFFFF. Then, if the counter is enabled, the 
count decrements by one at  the timer clock (TIMCLK) rising edge. Alternatively, writing to the Load 
Register (TimerXLoad) loads a new initial counter value.  Then, if the counter is enabled, the counter starts 
to decrement from this loaded value. 
In 32-bit mode, when the count reaches zero (0x00000000 ), an interrupt is generated. Then,...

 
3. Operation Description 
 
 Periodic Mode 
Writing to the Load Register (TimerXLoad) loads an  initial counter value. Then, the counter starts to 
decrement from this value if the counter is enabled. 
In 32-bit mode, all 32 bits of the counter are decremented. Then, when the count reaches zero (0x00000000), 
an interrupt is generated. The counter reloads the Lo ad Register value. The counter starts to decrement 
again. As long as the counter is enabled, this whole cycle is repeated.   
In 16-bit...

 
3. Operation Description 
 
 One-shot Mode 
To start the count down sequence in One-shot Mode, a new load value is written to the Load Register 
(TimerXLoad). If the counter is enabled, it starts to decrement from this value. 
In 32-bit mode, all 32 bits of the counter are decremented. Then, when the count reaches zero (0x00000000), 
an interrupt is generated. Then, the counter halts.   
In 16-bit mode, only the least significant 16 bits of  the counter are decremented. When the count reaches 
0x0000,...

 
3. Operation Description 
 
3.2. Default 
After the reset, the timer is initialized as shown below: 
  Timer counter disabled 
   Free-running mode selected 
   16-bit counter mode selected 
   Prescaler in the setting of dividing by 1 
   Interrupt clear and inte rrupt enable states 
   Load Register set to zero 
   Counter value set to 0xFFFFFFFF 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  12: Dual  Timer 
MN706-00002-1v0-E 
353 
MB9Axxx/MB9Bxxx  Series  

 
3. Operation Description 
 
3.3. Interrupt Behavior 
This section describes interrupt behaviors.   
An interrupt is generated when the counter reaches 0x00000000 (in 32-bit mode) or 0xXXXX0000 (in 
16-bit mode) in the setting of interrupt enable (IntEnable=1). In 16-bit mode, the most significant 16 bits of 
the counter are ignored.   
Writing to Interrupt Clear Register (T imerXIntClr) clears an interrupt.   
The interrupt signals generated in the Timer module can be masked when Interrupt Enable bit...