Fujitsu Series 3 Manual

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 Anomalous frequency detection 
Figure 5-3  provides an example of anomal ous frequency  detection operation. 
Figure 5-3 Example anomalous frequency detection operation 
Main clock
Divided clock of  High-speed CR
Count-up cycle
 
1.  This function detects rising edges of the divided clock of high-speed CR. 
2.  After detecting edges, it counts up clocks using the main clock. 
3.  It keeps counting up until it detects the next rising edge of the divided clock of high-speed...

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 Example anomalous frequenc y detection window setting 
The anomalous frequency detection counts up between edges of the divided clock of high-speed CR. The 
measurement interval is also affected by the accur acy of CR. When you configure the window register 
value, therefore, the CR accuracy mu st be considered for the value. 
For frequency accuracy of the CR oscilla tor, check the relevant data sheet. 
 Calculation method 
The count value range of anomalous frequency...

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Table 5-1 Example window settings Divided clock of High-speed CR  Main 
crystal 
oscillation  High-speed 
CR error Count value 
including 
high-speed CR  error  Lower limit of 
window set  value  Upper limit of 
window set  value 
Divide-by-1024 
clocks of CR:4MHz  4MHz ±5% 
975 ( 3.61MHz) - 
1078 (  4.42MHz)  926  
(
  3.43MHz)  1131  
(
  4.64MHz) 
 
CHAPTER  10: Clock  supervisor 
MN706-00002-1v0-E 
307 
MB9Axxx/MB9Bxxx  Series  

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6. Register list 
This section explains the register list of clock supervisor functions. 
 Register list 
Ta b l e  6 - 1  shows the register list. 
Table 6-1 Register list 
Abbreviation Register name See 
CVS_CTL CSV control register  6.1 
CVS_STR CSV status register  6.2 
FCSWH_CTL Frequency detection window setting register (Upper)  6.3 
FCSWL_CTL Frequency detection window setting register (Lower)  6.4 
FCSWD_CTL Frequency detection counter register  6.5 
 
CHAPTER...

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6.1.  CSV control register (CSV_CTL) 
The CSV_CTL register configures the control of CSV function. 
 Register configuration 
bit  15 14 13 12  11 10  9 8 
Field Reserved FCD Reserved FCSRE FCSDE
Attribute -  R/W - R/W R/W 
Initial value  1b0  3b111  2b00 1b0 1b0 
           
bit  7 6 5 4 3  2 1 0 
Field Reserved  SCSVE MCSVE
Attribute -  R/W R/W 
Initial value  6b000000 1b1 1b1 
 Register functions 
[bit 15] Reserved bit 
0b0 is read from these bits. 
Set these bits to...

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[bit 8] FCSDE: FCS function enable bit 
bit Description 
When 0 is written The FCS function is disabled [Initial value] 
When 1 is written  The FCS function is enabled. 
When read The register value is read. 
 
[bits 7:2] Reserved bits  0b000000 is read from these bits. 
Set these bits to 0b000000 when writing. 
[bit 1] SCSVE: Sub CSV function enable bit 
bit Description 
When 0 is written  The sub CSV function is disabled 
When 1 is written The sub CSV function is enabled....

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6.2.  CSV status register (CSV_STR) 
The CSV_STR register indicates the status of CSV function. 
 Register configuration 
bit  7 6 5 4 3  2 1 0 
Field Reserved  SCMF MCMF
Attribute -  R R 
Initial value  6b000000 1b0 1b0 
 Register functions 
[bits 7:2] Reserved bits 
0b000000 is read from these bits. 
Set these bits to 0b000000 when writing. 
[bit 1] SCMF : Sub clock failure detection flag 
bit Description 
When written  No effect 
When 0 is read  No sub clock failure...

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6.3.  Frequency detection window setting register (Upper) (FCSWH_CTL) 
The FCSWH_CTL register configures the frequency detection window setting register 
(Upper). 
 Register configuration 
bit  15         0 
Field FWH 
Attribute R/W 
Initial value  160xFFFF 
 Register functions 
[bits 15:0] FWH: Frequency detection window setting bits (Upper) 
bits 15:0  Description 
When written Any value can be written to these bits. 
When read The register value is read. 
 
 
  Set a...

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6.4.  Frequency detection window setting register (Lower) (FCSWL_CTL) 
The FCSWL_CTL register configures the frequency detection window setting register (Lower). 
 Register configuration 
bit  15         0 
Field FWL 
Attribute R/W 
Initial value  160x0000 
 Register functions 
[bits 15:0] FWL: Frequency detection window setting bits (Lower) 
bits 15:0  Description 
When written Any value can be written to these bits. 
When read The register value is read. 
 
 
  Set a...

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6.5.  Frequency detection counter register (FCSWD_CTL) 
The FCSWD_CTL register indicates the counter value of frequency detection using the main 
clock. 
 Register configuration 
bit  15         0 
Field FWD 
Attribute R 
Initial value  160x0000 
 Register functions 
[bits 15:0] FWD: Frequency detection count data 
bits 15:0  Description 
When written No effect 
When read The count value is read. 
 
 
  This  reg

ister retains the count value when detecting an error. 
...