Fujitsu Series 3 Manual

 
4. Setting Procedure Example 
 
4.  Setting Procedure Example 
This chapter describes an example of the Dual Timer setting procedure.   
 Dual Timer Setting Procedure Flow 
Figure 4-1 Periodic Mode Setting Procedure Example 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
Start setting 
// Register setting example 
 
Interrupt source clear  // TimerXIntClr =0xF

FFF FFFF 
 
Timer mode setting 
Counter size setting  Prescaler setting Interrupt enable // Mode: Periodic Mod e
  
// Size: 32bit counter 
// Prescaler:...

 
4. Setting Procedure Example 
 
 Timer Interval Setting 
Expressions of the timer interval calcula tions in respective modes are shown in Table 4-1:  
Table 4-1 Expression for Timer Interval Calculation 
Mode Timer Interval 
32-bit Free-running    (PRESCALEDIV / TIMCLKFREQ)  232 
16-bit Free-running 
(PRESCALEDIV / TIMCLKFREQ)  216 
Periodic & One-shot 
(PRESCALEDIV / TIMCLKFREQ)  TimerXLoad 
 
  TIMCLK
FREQ is the timer clock (TIMCLK) frequency.   
   PRESCALE
DIV is the prescaler division...

 
5. Register 
 
5. Register 
This chapter describes the structures and functions of the registers used in Dual Timer. 
 Dual Timer Register List 
 
Abbreviation Register  Name See 
Timer1Load Timer1 Load Register  5.1 
Timer1Value Timer1 Value Register  5.2 
Timer1Control Timer1 Control Register  5.3 
Timer1IntClr Timer1 Interrupt Clear Register  5.4 
Timer1RIS Timer1 Interrupt Status Register  5.5 
Timer1MIS Timer1 Masked Interrupt Status Register  5.6 
Timer1BGLoad Timer1 Background Load Register...

 
5. Register 
 
5.1.  Load Register (TimerXLoad)    X=1 or 2 
Load Register (TimerXLoad) has a start value to decrement the counter in 32-bit Register. 
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXLoad[31:16] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field TimerXLoad[15:0] 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/WR/W R/W R/W R/W R/W R/W
Initial 
value  0 0 0...

 
5. Register 
 
5.2.  Value Register (TimerXValue)    X=1 or 2 
Value Register (TimerXValue) indicates the current value of the decrement counter in 32-bit 
Read Only Register. 
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXValue[31:16] 
Attribute  R R R R R R R R R R R R R R R R 
Initial 
value  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field TimerXValue[15:0] 
Attribute  R R R R R R R R R R R R R R R R 
Initial 
value  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

 
5. Register 
 
5.3.  Control Register (TimerXControl)    X=1 or 2 
Control Register (TimerXControl) controls the Timer.   
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field Reserved 
Attribute  - - -  - - - - - - - - - - - - - 
Initial 
value  X X X X X X X X X X X X X X X X 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved  Timer
En Timer
Mode
Int
EnableReser ved TimerPre  Timer
Size One
Shot
Attribute  - - - - - - - -  R/W 
Initial 
value  X X X X X X X X 0 0 1 0 0 0 0 0 
 
[bit31:8]...

 
5. Register 
 
[bit3:2] TimerPre : Prescale bit 
bit3 bit2 Description 
0 0 Clock divided by 1 [Initial value] 
0  1 Clock divided by 16 
1  0 Clock divided by 256 
1  1 Undefined, do not use 
 
[bit1] TimerSize : Counter size bit  Select 16/32-bit counter operation. 
bit Description 
0  16-bit counter [Initial value] 
1 32-bit counter 
 
[bit0] OneShot : One-shot mode bit  Select One-shot Mode or Counter Wrapping Mode (Free-running Mode/Periodic Mode). Based on Mode bit 
(TimerMode) settings,...

 
5. Register 
 
5.4.  Interrupt Clear Register (TimerXIntClr)    X=1 or 2 
Interrupt Clear Register (TimerXIntClr) clears an interrupt. 
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXIntClr[31:16] 
Attribute  W W W  W W WWWWWWWW W WW
Initial 
value  X X X X X X X X X X X X X X X X 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field TimerXIntClr[15:0] 
Attribute  W W W  W W WWWWWWWW W WW
Initial 
value  X X X X X X X X X X X X X X X X 
 
[bit31:0] TimerXIntClr  : Interrupt clear bit 
Writing...

 
5. Register 
 
5.5.  Interrupt Status Register (TimerXRIS)    X=1 or 2 
Interrupt Status Register (TimerXRIS) indicates an unmasked and raw interrupt status. 
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field Reserved 
Attribute  - - -  - - - - - - - - - - - - - 
Initial 
value  X X X X X X X X X X X X X X X X 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved  Timer
XRIS
Attribute  - - -  - - - - - - - - - - - -  R 
Initial 
value  X X X X X X X X X X X X X X X 0 
 
[bit31:1] Reserved :...

 
5. Register 
 
5.6.  Masked Interrupt Status Register (TimerXMIS) X=1 or 2 
Masked Interrupt Status Register (TimerXMIS) indicates the masked interrupt status. 
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field Reserved 
Attribute  - - -  - - - - - - - - - - - - - 
Initial 
value  X X X X X X X X X X X X X X X X 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved  Timer
XMIS
Attribute  - - -  - - - - - - - - - - - -  R 
Initial 
value  X X X X X X X X X X X X X X X 0 
 
[bit31:1] Reserved :...