Fujitsu Series 3 Manual

 
5. Base Timer Interrupt 
 
5.  Base Timer Interrupt 
This section provides a list of interrupt request flags, interrupt enable bits, and interrupt 
causes for each function of the base timer. 
 Interrupt control bits and in terrupt causes for each function 
Ta b l e  5 - 1 shows the interrupt control bits and interrupt causes for each function. 
Table 5-1 Interrupt control bits and interrupt causes in each mode 
Status Control Register (STC) 
 Interrupt 
request flag bit Interrupt request 
enable bit...

 
6. Starting the DMA Controller (DMAC) 
 
6.  Starting the DMA Controller (DMAC) 
The DMAC can be started using the generation of an interrupt request by the base timer. 
 DMA transfer operation using interrupt causes of the base timer 
The DMAC can be started using the generation of an interrupt cause by the base timer.  Figure 6-1 gives an 
overview o
f starting the DMAC using the base timer. 
Figure 6-1 Overview of starting the DMAC using the base timer 
 
Base timer
CPU
DMAC
Use of the DMAC
(1)...

 
7. Base Timer Registers 
 
7.  Base Timer Registers 
This section provides register lists of the base timer in each mode. 
 List of registers used when  the 16-bit PWM timer is selected 
Table 7-1 List of registers used when the 16-bit PWM timer is selected 
Abbreviation Register name See 
TMCR Timer  Control Register  9.1.6 
TMCR2 Timer Control Register 2  9.1.6 
STC Status Control Register  9.1.6 
PCSR PWM Cycle Set Register  9.1.7 
PDUT PWM Duty Set Register  9.1.8 
TMR Timer Register  9.1.9 
 
...

 
8. Notes on using the base timer 
 
8.  Notes on using the base timer 
This section provides notes on using the base timer. 
 Notes on setting the program  common to each timer 
  It is prohibited to rewrite the following bits in  the TMCR2 and TMCR registers during operation. 
Rewriting of the bits must be performed befo re starting or after stopping the operation. 
[TMCR2 bit 8], [TMCR bit 14, 13, 12]  CKS3 to CKS0 : Clock selection bits 
[bit 10, 9, 8]  EGS2, EGS1, EGS0 : Measurement edge...

 
9. Descriptions of base timer functions 
 
9.  Descriptions of base timer functions 
This section explains each function of the base timer. 
 Base timer functions 
1.  PWM timer function 
2.  PPG timer function 
3.  Reload timer function 
4.  PWC timer function 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  14-2: Base Timer 
MN706-00002-1v0-E 
429 
MB9Axxx/MB9Bxxx  Series  

 
9. Descriptions of base timer functions 
 
9.1.  PWM timer function 
The function of the base timer can be set to either the 16-bit PWM timer, 16-bit PPG timer, 
16/32-bit reload timer, or 16/32-bit PWC timer using the FMD2, 1, and 0 bits in the Timer 
Control Register. This section explains the timer functions available when PWM is set. 
1. 16-bit PWM timer operations 
2.  One-shot operation 
3.  Interrupt causes and timing chart 
4.  Output waveforms 
5.  PWM timer operation flowchart 
6.  Timer...

 
9. Descriptions of base timer functions 
 
9.1.1. 16-bit PWM timer operations 
In PWM timer operations, waveforms in the specified cycle from the detection of a trigger can 
be output in one-shot or continuously. 
The cycle of the output pulse can be controlled by changing the PCSR value. 
The duty ration can be controlled by changing the PDUT value. 
After writing data to the PCSR, be sure to write it to the PDUT. 
 Continuous operation 
  When a restart is disabled (RTGEN = 0) 
Figure 9-1 PWM...

 
9. Descriptions of base timer functions 
 
9.1.2. One-shot  operation 
In one-shot operation, a single pulse of any width can be output using a trigger. When a 
restart is enabled, the counter is reloaded when an edge is detected during operation. 
 One-shot operation 
  When a restart is disabled (RTGEN = 0) 
Figure 9-3 One-shot operation timing chart (trigger restart is disabled) 
 
Rising edge detection The trigger is ignored.
Trigger
m
n
 
o
(1)  
(2) 
PWM 
output 
waveform
(1) = T(n+1)ms
(2) =...

 
9. Descriptions of base timer functions 
 
9.1.3. Interrupt causes and timing chart 
This section explains interrupt causes and a timing chart. 
 Interrupt causes and timing char t (PWM output: Normal polarity) 
As a time from trigger input to loading of the counter va lue, T is required for software triggering or 2T to 
3T (T: machine cycle) fo r external triggering. 
Figure 9-5  shows the interrupt causes and a timing chart wher e the cycle set value = 3 an
d duty value
  = 1. 
Figure 9-5 Interrupt...

 
9. Descriptions of base timer functions 
 
9.1.4. Output  waveforms 
This section explains the PWM output. 
 How to make an all-LOW or all-HIGH PWM output 
Figure 9-6  shows how to make all-LOW PWM output and  Figure 9-7 shows how to make all-HIGH output. 
Figure 9-6 Example of outputting all-LOW level waveforms as PWM output 
 
Duty value
PWM output 
waveform
0x00020x00010x0000
The duty value is 
reduced gradually.0xXXXX
Underflow interrupt
An underflow interrupt sets the PMSK 
to 1.
The output...