Fujitsu Series 3 Manual

 
9. Descriptions of base timer functions 
 
 Underflow operation 
An underflow occurs when the count er value changes from 0x0000 to 0xFFFF. Therefore, an underflow 
occurs at a count of [Set value in the PWM Cycle Set Register + 1]. 
When an underflow occurs, the contents of the PWM Cycle Set Register (PCSR) are loaded to the counter. 
When the MDSE bit in the Timer Control Register (TM CR) is 0, the count operation continues. When the 
MDSE bit is 1, the counter stops wh ile keeping the loaded...

 
9. Descriptions of base timer functions 
 
 Operation of the  input pin function 
The TGIN pin can be used for trigger input. When a valid edge is input to the TGIN pin, the contents of the 
PWM Cycle Set Register are loaded to  the counter and the count operation is started. As a time from trigger 
input to loading of the counter value, 2T to 3T (T: machine cycle) is required. 
Figure 9-15  shows a trigger input operation performed when a rising edge is specified as a valid edge. 
Figure 9-15...

 
9. Descriptions of base timer functions 
 
9.3.2. Reload timer operation flowchart 
This section provides an operation flowchart of the reload timer. 
 Reload timer operation flowchart 
 
  
Reload mode selection
Count clock selection
Operation mode selection
Interrupt flag clear
Interrupt enableSettings
 
One-shot operation
Continuous operation 
External trigger detection 
 TGIR flag setting
 
Start of decrement
Occurrence of an  underflow 
 UDIR flag setting
MDSE = 0? 
No
Software trigger...

 
9. Descriptions of base timer functions 
 
9.3.3. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the reload 
timer is selected 
The Timer Control Register (TMCR) controls timer operations. 
 Timer Control Register (H igh-order bytes of TMCR) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS2 CKS1 CKS0 res EGS1 EGS0 
Attribute  R/W R/W R/W  R/W R/W R/W R/W 
Initial value  0 0 0  0 0b00  0 0 
 
[bit 15] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit...

 
9. Descriptions of base timer functions 
 
[bit 9:8] EGS1, EGS0: Trigger input edge selection bits   These bits select a valid edge for  input waveforms as an external start cause and set the trigger condition. 
   When the initial value or 0b00 is set, the timer is not started by external waveforms because the setting 
means that no valid edge is selected for input waveforms. 
 
If the STRG 

bit is set to 1, software triggering  is enabled regardless 
 of the EGS1 and EGS0 settings. 
 
  Changes...

 
9. Descriptions of base timer functions 
 
 Timer Control Register 2 (Low-order bytes of TMCR) 
 
bit 7 6 5 4 3 2 1 0 
Field T32 FMD2 FM D1 FMD0 OSEL MDSE CTEN STRG 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] T32: 32-bit timer selection bit    This bit selects the 32-bit timer function. 
   When the FMD2, FMD1, and FMD0 bits are set to 0b011 to select the reload timer function, setting the 
T32 bit to 1 selects 32-bit timer mode. 
   Changes must be made...

 
9. Descriptions of base timer functions 
 
[bit 3] OSEL: Output polarity specification bit   This bit selects whether to invert the timer output level. 
   Used in combination with bit 2 MDSE, this bit generates the following output waveforms. 
MDSE OSEL  Output waveforms 
0 0  Toggle output at the LOW level at the start of counting 
0 1  Toggle output at the HIGH level at the start of counting 
1 0  Rectangular waves at the HIGH level during counting 
1 1  Rectangular waves at the LOW level during...

 
9. Descriptions of base timer functions 
 
[bit 0] STRG: Software trigger bit   When the CTEN bit is 1, writing 1 to the STRG bit enables software triggering. 
   The read value of the STRG bit is always 0. 
 
  Soft ware triggering

 is also enabled when 1 is  written to the CTEN and
  STRG bits simultaneously. 
   If the STRG bit is set to 1, software triggering  is enabled regardless of the EGS1 and EGS0 settings. 
 
Bit Description 
0 Invalid 
1 Start triggered by software 
 
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9. Descriptions of base timer functions 
 
 Timer Control Register 2 (High-order bytes of TMCR2) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS3 
Attribute R/W  R/W 
Initial value 0b0000000  0 
Note:  This register is placed above the STC register. 
[bit 15:9] res: Reserved bits  The read value is 0. 
Set 0 to this bit. 
 
[bit 8] CKS3: Count clock selection bit  See Count clock selection bit in  9.3.3 Timer Control Register (High-order bytes of TMCR). 
 
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9. Descriptions of base timer functions 
 
 Status Control Register (STC) 
 
bit 7 6 5 4 3 2 1 0 
Field res TGIE res UDIE res TGIR res UDIR 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
Note:  The TMCR2 register is placed in the upper bytes of this register. 
[bit 7] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 6] TGIE: Trigger interrupt request enable bit    This bit controls interrupt requests of bit 2 TGIR. 
   When the TGIE bit is enabled,...