Fujitsu Series 3 Manual

 
1. Overview of Multifunction Timer 
 
CHAPTER: Multifunction Timer 
This chapter describes the multifunction timer unit. 
 
1.
 Overview of Multifunction Timer 
2. Configuration of Multifunction Timer 
3. Operations of Multifunction Timer 
4. Registers of Multifunction Timer 
5. Other Matters 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFMFT-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
495 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview of Multifunction Timer 
 
1.  Overview of Multifunction Timer 
The multifunction timer is a function block that enables three-phase motor control. In conjunction 
with PPG and ADC, it can provide a variety of motor controls. An overview of the multifunction 
timer is provided below. 
  Functions 
The multifunction timer has the following functions. 
  It can output PWM signals with any cycle/pulse length (PWM signal output function). 
   It can start PPG in synchronization with PWM...

 
2. Configuration of Multifunction Timer 
 
2.  Configuration of Multifunction Timer 
This chapter describes the configuration of the multifunction timer and the functions of each 
function block and I/O pin. 
 
2.1 Block Diagram of Multifunction Timer  
2.2  Description of Each Function Block  
2.3  I/O Pins of Multifunction Timer Unit 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
497 
MB9Axxx/MB9Bxxx  Series  

 
2. Configuration of Multifunction Timer 
 
2.1.  Block Diagram of Multifunction Timer 
 Block Diagram 
Figure 2-1  shows the block diagram of the entire function timer. 
Figure 2-1 Block Diagram of Multifunction Timer 
 
3 ADC2 start trigger
from FRT0, FRT1,FRT2
3 ADC1 start trigger
from FRT0, FRT1,FRT2
RT0
RT1
RT2
RT3
RT4
RT5
3 PPG sig.
(from PPG )
3 ADC0 start trigger
from FRT0, FRT1,FRT2ADC0 scan start trigger
RTO0 output port
IC0 input port
ch.0
ch.10
from other
MFT-FRT
ch.1FRTS    
ch.2
ch.32...

 
2. Configuration of Multifunction Timer 
 
2.2.  Description of Each Function Block 
 FRT: 3ch. 
  FRT is a timer function block that  outputs the reference counter value for the operation of each function 
block in MFT. 
   FRT consists of a clock pre-scaler ., 16-bit Up/Down counter, cycle se tting register (TCCP register) and 
controller.  Figure 2-2 shows the configuration of FRT. 
   The cl ock pre-
scal

er divides the peripheral clock (PCLK) signal in LSI to generate the operating clock 
for...

 
2. Configuration of Multifunction Timer 
 
 OCU: 6ch. (2ch. ×3) 
  OCU is a function block that generates and outputs PWM signals based on the counter value of FRT. The 
signal names of PWM signals output by OCU are RT0 to RT5. These signals are output to LSI’s external 
output pins via WFG. 
   OCU consists of FRTS, compare value store register (OCCP register) and controller. The basic unit is in 
a 2-channel configuration with  two sets of each circuit. Figure 2-3 shows the configuration of OCU....

 
2. Configuration of Multifunction Timer 
 
 WFG: 3ch 
  WFG is a function block that is located at the back of OCU and generates signal waveforms for motor 
control from the RT0 to RT5 and PPG signals (PPG is located outside the multifunction timer). 
   The signal outputs to LSI external pins from WFG are called RTO0 to RTO5. They are divided into 
blocks: the block that outputs RTO0 and RTO1 from RT0 and RT1; the block that outputs RTO2 and 
RTO3 from RT2 and RT3; and the block that outputs RTO4...

 
2. Configuration of Multifunction Timer 
 
 NZCL 
  NZCL is a function block that performs noise cancella tion to the external interrupt input signal (DTTIX 
signal) for emergency shutdown of the motor and generates DTIF interrupts to CPU. 
   NZCL consists of a noise canceller and controller. 
   It can be switched to the state of  the GPIO port which is also used for WFG’s external output signals 
(RTO0 to RTO5) using the selection function of the I/O port block while DTIF interrupt is being...

 
2. Configuration of Multifunction Timer 
 
 ICU: 4ch. (2ch. ×2) 
  ICU is a function block that captures the FRT count value and generates an interrupt to CPU when a 
valid edge is detected at an external input pin signal. 
   ICU consists of FRTS, edge detector, 16-bit capture register and control register. Its basic unit is in a 
2-channel configuration with  two sets of each circuit. Figure 2-6 shows the configuration of ICU. 
   FR TS is a circuit that selects th
e coun

ter valu e of the FRT...

 
2. Configuration of Multifunction Timer 
 
 ADCMP: 3ch. 
  ADCMP is a function block that generates AD conver sion start signals at any timing of FRT cycle. 
   ADCMP is in a 3-channel configuration with each corr esponding to one of the 3 units of ADC mounted. 
   ADCMP consists of FRTS, two 16-bit compare regi sters (ACCP register and ACCPDN register) and 
control register.  Figure 2-7 shows the configuration of ADCMP and ATSA. 
   FRTS is a circuit that selects th e coun

ter value of the FRT...