Fujitsu Series 3 Manual

 
4. Registers of Multifunction Timer 
 
Figure 4-2 FRT Counter Start and Stop (Up/Down-count Mode) 
 
FUJITSU SEMICONDUCTOR LIMITED 
 
FRT counter start , clear, stop ( up-down-count mode)
0x0000 
PEAK (=TCCP) 
FRT count time
  Start FRT (STOP=0, SCLR=0 )
Stop FRT (ST O

P=1, SCLR=1, TCDT=0x0000 )   
 
 
[bit7] TCSA.BFE 
Process Value  Function 
0 Disables TCCP’s buffer function. Write 
1 Enables TCCP’s buffer function. 
Read - Reads the register setting. 
 
TCSA.BFE is a register that specifies...

 
4. Registers of Multifunction Timer 
 
TCSA.ICLR is a register that is set to 1 when a match is detected between FRT’s count value and TCCP 
value during FRT operation (hereinafter  referred to as Peak value detection. 
By reading this register, whether FRT’s count value ha s reached the TCCP value or not can be determined. 
This register can be cleared by writing 0. 
This register does nothing, if 1 is written. Always  write 1 to the register when rewriting to another 
register in the same address...

 
4. Registers of Multifunction Timer 
 
1 is always read from this register at RMW access. 
See 5.2 Treatment of Event Detect Register and Interrupt . 
[bit15] TCSA.ECKE 
Process Value  Function 
0 Uses the internal clock (PCLK) as FRT’s count clock. Write 
1 Uses an external input clock (FRCK) as FRT’s count clock. 
Read - Reads the register setting. 
 
TCSA.ECKE is a register that selects the clock signal to be used as FRT’s count clock. 
Change the setting of this register while FRT is stopping. 
To...

 
4. Registers of Multifunction Timer 
 
4.3.2. FRT Control Register B (TCSB) 
TCSB is a 16-bit register that controls FRT. 
Each mounted channel has three registers: TCSB0, TCSB1 and TCSB2. 
TCSB0 controls FRTch0. 
TCSB1 controls FRTch1. 
TCSB2 controls FRTch2. 
 Configuration of Register 
Bit  15 14 13  12 11 10  9 8 
Field Reserved 
Attribute - 
Initial Value  0 0 0  0 0 0 0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field Reserved  AD2E AD1E AD0E 
Attribute -  R/W R/W R/W 
Initial Value  0 0 0  0 0 0 0 0...

 
4. Registers of Multifunction Timer 
 
TCSB.AD0E, TCSB.AD1E and TCSB.AD2E are registers that select AD conversion start signal output 
upon Zero value detection by FRT. 
These registers are used to start ADC conversion upon Zero value detection by FRT. Each of the AD 
conversion start signals for the 3 channels of FRT undergoes logic OR by ADC unit to which they are to be 
output. See the entire block diagram. 
The conversion start signal from FRT ch.0, FRTch.1 and FRTch.2 to ADCunit0 has undergone...

 
4. Registers of Multifunction Timer 
 
4.3.3. FRT Cycle Setting Register (TCCP) 
TCCP is a 16-bit register that sets FRT’s count cycle. 
Each mounted channel has three registers: TCCP0, TCCP1 and TCCP2. 
TCCP0 sets the cycle for FRTch0. 
TCCP1 sets the cycle for FRTch1. 
TCCP2 sets the cycle for FRTch2. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
Bit  15 14 13 12  11 10 9 8 7 6 5 4 3 2 1 0 
Field TCCP[15:0] 
Attribute R/W 
Initial  Va l u e   1 1...

 
4. Registers of Multifunction Timer 
 
Figure 4-4 shows an example of changing FRT’s cy cle when the buffer fun ction is enabled. 
When TCCP’s buffer function is enabled, a value writte n to the buffer register is transferred to the TCCP 
register upon the next Zero value detection. FRT’s c ount cycle is changed in the next FRT cycle after the 
writing. 
Figure 4-4 Example of Changing FRT’s Cycle (When Buffer Function is Enabled) 
 
FRT count
0x0000
0xFFFF
time
TCSA.BFE=1, TCCP Buffer reg. enable...

 
4. Registers of Multifunction Timer 
 
4.3.4. FRT Count Value Register (TCDT) 
TCDT is a 16-bit register that reads and writes FRT’s count value. 
Each mounted channel has three registers: TCDT0, TCDT1 and TCDT2. 
TCDT0 is the timer count value of FRT-ch.0. 
TCDT1 is the timer count value of FRT-ch.1. 
TCDT2 is the timer count value of FRT-ch.2. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
Bit  15 14 13 12  11 10 9 8 7 6 5 4 3 2 1 0 
Field...

 
4. Registers of Multifunction Timer 
 
4.3.5. OCU Connecting FRT Select Register (OCFS) 
OCFS is an 8-bit register that selects and sets FRT to be connected to OCU. 
Each mounted channel has three registers: OCFS10, OCFS32 and OCFS54. 
OCFS10 controls OCU ch1 and OCU ch0. 
OCFS32 controls OCU ch3 and OCU ch2. 
OCFS54 controls OCU ch5 and OCU ch4. 
OCFS10 and OCFS54 are located at even-numbered addresses, while OCFS32 is located at 
an odd-numbered address. Therefore, their bit positions are [7:0] and...

 
4. Registers of Multifunction Timer 
 
4.3.6. OCU Control Register A (OCSA) 
OCSA is an 8-bit register that control OCU’s operation. 
Each mounted channel has three registers: OCSA10, OCSA32 and OCSA54. 
OCSA10 controls OCU ch1 and OCU ch0. 
OCSA32 controls OCU ch3 and OCU ch2. 
OCSA54 controls OCU ch5 and OCU ch4. 
 Configuration of Register 
Bit  7 6 5  4 3 
2 1 
0 
Field IOP1  IOP0 IOE1  IOE0 BDIS1  BDIS0  CST1 CST0 
Attribute  R/W R/W R/W R/W  R/W R/W R/W R/W 
Initial Value 0 0 0 0  1 1 0 0 
 
...