Fujitsu Series 3 Manual

 
4. Registers of Multifunction Timer 
 
The table below shows examples of DCK[2:0] settings and the count clock cycle of the WFG timer. 
Count Clock Cycle of WFG Timer 
DCK[2:0] Clock 
Ratio  PCLK=25ns 
(40MHz)  PCLK=33.3ns 
(33MHz)  PCLK=50ns 
(25MHz) 
000  1  25ns 30ns 50ns 
001 2  50ns 61ns 100ns 
010 4  100ns 121ns 200ns 
011 8  200ns 242ns 400ns 
100 16  400ns 485ns 800ns 
101 32  800ns 970ns 
1.6s 
110 64  1.6μs 1.9 μs 
3.2s 
 
[bit5:3] WFSA.TMD[2:0] 
Process Value  Function 
000 Sets WFG’s...

 
4. Registers of Multifunction Timer 
 
WFSA.GTEN[1:0] is a register that selects the output condition of the CH_GATE for each channel of WFG, 
in combination with WFSA.TMD[2:0]. 
This register has no meaning, wh en WFSA.TMD[2:0] is set to 000,100,. Change the setting, while OCU 
and PPG timer units to be  connected are stopping. 
The CH_GATE signal is generated based on the RT  input signal and WFG timer operation at each channel 
of WFG (for details, see  4.5 Details of WFG Output Waveform ).  
The...

 
4. Registers of Multifunction Timer 
 
The following section describes the configuration and operation of the PPG selector. 
Each channel of WFG can output a trigger signal (CH_GATE signal) to start the PPG timer unit. 
The CH10_GATE signal, CH32_GATE signal and CH54_GATE signal refer to the GATE signal for each 
channel of WFG, which has been generated at WFG ch10, WFG ch32 and WFG ch54, respectively. 
After its output is selected by WFSA.PSEL[1:0] for each PPG timer unit to be connected, each CH_GATE...

 
4. Registers of Multifunction Timer 
 
[bit11:10] WFSA.PGEN[1:0] 
Process Value Function 
00 Does not reflect the CH_PPG signa l on WFG output (RTO output). 
Write 
Other 
than 
above  Specifies the condition to be used to reflect the CH_PPG signal on WFG 
output. 
For details of the reflection conditions, see 4.5
 Details of WFG Output 
Wa v e f o
r

m . 
Read  - Reads the register setting. 
 
WFSA.PGEN[1:0] is a register that  specifies how to reflect the CH_PPG signal that is input to each channel...

 
4. Registers of Multifunction Timer 
 
4.3.11.  WFG Timer Value Register (WFTM) 
WFTM is a 16-bit register that sets the initial value of the WFG timer. 
Each mounted channel has three registers: WFTM10, WFTM32 and WFTM54. 
WFTM10 sets the initial value of the WFG timer for WFG ch10 (the output processing block of 
OCU ch1 and ch0). 
WFTM32 sets the initial value of the WFG timer for WFG ch32 (the output processing block of 
OCU ch3 and ch2). 
WFTM54 sets the initial value of the WFG timer for WFG ch54...

 
4. Registers of Multifunction Timer 
 
4.3.12.  NZCL Control Register (NZCL) 
NZCL is a 16-bit register that controls DTIF interrupt (interrupt for emergency motor shutdown 
by signal input from the DTTIX pin). 
  It should be noted that this register does not allow for byte access. 
 Configuration of Register 
 
Bit 15 14 13 12 11 10 9 8 
Field Reserved 
Attribute - 
Initial Value  0 0 0  0 0 0 0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field Reserved  SDTI NWS[2:0]  DTIE 
Attribute -  W R/W  R/W...

 
4. Registers of Multifunction Timer 
 
Figure 4-7 shows a block diagram and time chart of the DTIX pin and DTIF interrupt. 
Figure 4-7 Block Diagram and Time Chart of DTIX Pin and DTIF Interrupt 
 
NZCL
Noise cancellerDTTIX
input portDTIF interrupt
RTO0 ～RTO5
GPIO
RTO0～RTO5
output portWFG
Interrupt controller
DTTIX input signal
DTIF interrupt
Noize cancel operation
RTO0~RTO5 port
MFT-RTO outputGPIO-Motor Stop level Output(Hiz)
▲DTIF Interrupt assert ▲DTIF interrupt clear
OCU
MFTMotor Stop level
MFT-RTO...

 
4. Registers of Multifunction Timer 
 
Ta b l e  4 - 5 shows a list of function se ttings of the GPIO p in. 
PFR, DDR and PDOR in the table refer to the corresponding  registers of the GPIO port that are shared with 
the RTO0 to RTO5 pins.   
Table 4-5 Setting List of Motor Non-operating Level by DTTIX Pin Interrupt 
Setting of GPIO Register 
 
PFR EPFR1 
[11:0]  EPFR1
[12]  DDRPDOR DTIF 
Signal  Level  State of RTO Pin 
0 
Output RTO0 to RTO5 1 1 
1 Output High level 
0 Output RTO0 to RTO5 1 0 
1...

 
4. Registers of Multifunction Timer 
 
[bit3:1] NZCL.NWS[2:0] 
Process Value Function 
000 DTIF interrupt is generated immediately after Low-leve input from the 
DTTIX pin. 
(No noise-canceling) 
001 
Sets the noise-canceling width to 4 PCLK cycles. 
010 Sets the noise-canceling width to 8 PCLK cycles. 
011 Sets the noise-canceling width to 16 PCLK cycles. 
100 Sets the noise-canceling  width to 32 PCLK cycles. 
Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting....

 
4. Registers of Multifunction Timer 
 
4.3.13.  WFG Interrupt Control Register (WFIR) 
WFIR is a register that controls DTIF interrupt and the interrupt from the WFG timer. 
This register is a special register dedicated to interrupt control, and each register bit is 
configured so that its state is not affected by writing 0. 
For this reason, reading before writing to the register is not required. Also, each register bit is 
configured so that its state is not affected by writing the read value back....