Fujitsu Series 3 Manual

 
9. Descriptions of base timer functions 
 
 Timer Control Register (L ow-order bytes of TMCR) 
 
bit 7 6 5 4 3 2 1 0 
Field res FMD2 FMD1 FMD0 OSEL  MDSE CTEN STRG 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 6:4] FMD2 to FMD0: Timer function selection bits    These bits select the timer function. 
   When the FMD2, FMD1, and FMD0 bits are set to 0b010, the PPG function is selected. 
...

 
9. Descriptions of base timer functions 
 
[bit 2] MDSE: Mode selection bit   This bit selects continuous pulse output or one-shot pulse output. 
   Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make 
changes at the same time you set 1 to the CTEN bit. 
Bit Description 
0 Continuous  operation 
1 One-shot operation 
 
[bit 1] CTEN: Count operation enable bit    This bit enables the operation of the down counter. 
   When the counter is in operation en abled...

 
9. Descriptions of base timer functions 
 
 Timer Control Register 2 (High-order bytes of TMCR2) 
 
bit 15 14 13 12 11 10 9 8 
Field res CKS3 
Attribute R/W  R/W 
Initial value 0b0000000  0 
Note:  This register is placed above the STC register. 
[bit 15:9] res: Reserved bits  The read value is 0. 
Set 0 to this bit. 
 
[bit 8] CKS3: Count clock selection bit  See Count clock selection bit in  9.2.6 Timer Control Register (High-order bytes of TMCR). 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  14-2:...

 
9. Descriptions of base timer functions 
 
 Status Control Register (STC) 
 
bit 7 6 5 4 3 2 1 0 
Field res TGIE res UDIE res TGIR res UDIR 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
Note:  The TMCR2 register is placed in the upper bytes of this register. 
[bit 7] res: Reserved bit  The read value is 0. 
Set 0 to this bit. 
 
[bit 6] TGIE: Trigger interrupt request enable bit    This bit controls interrupt requests of bit 2 TGIR. 
   When the TGIE bit is enabled,...

 
9. Descriptions of base timer functions 
 
[bit 2] TGIR: Trigger interrupt request bit   When a software trigger or trigger input is detected, the TGIR bit is set to 1. 
   The TGIR bit is cleared by writing 0. 
   Even if 1 is written to the TGIR  bit, the bit value is not affected. 
   The read value of read-modify-write instructions is 1 regardless of the bit value. 
Bit Description 
0  Clears an interrupt cause. 
1 Detects an interrupt cause. 
 
[bit 1] res: Reserved bit  The read value is 0....

 
9. Descriptions of base timer functions 
 
9.2.7. LOW Width Reload Register (PRLL) 
The LOW Width Reload Register (PRLL) is a register used to set the LOW width of PPG 
output waveforms. Transfer to the Timer Register is performed at detection of a start trigger or 
at an underflow after the completion of HIGH width counting. 
 bit 15       0 
Field PRLL [15:0] 
Attribute R/W 
Initial value  0xXXXX 
 
This register is used to set the LOW width of PPG output waveforms. Transfer to the Timer Register is...

 
9. Descriptions of base timer functions 
 
9.2.8. HIGH Width Reload Register (PRLH) 
The HIGH Width Reload Register (PRLH) is a buffered register used to set the HIGH width of 
PPG output waveforms. Transfer from the PRLH to the buffer register is performed at 
detection of a start trigger and at an underflow after the completion of HIGH width counting. 
Transfer from the buffer register to the Timer Register is performed at an underflow at the 
completion of LOW width counting. 
 bit 15       0 
Field...

 
9. Descriptions of base timer functions 
 
9.2.9. Timer  Register  (TMR) 
The Timer Register (TMR) reads the value of the 16-bit down counter. 
 bit 15       0 
Field TMR [15:0] 
Attribute R 
Initial value  0x0000 
 
The value of the 16-bit down counter is read. 
   Access the TMR register with 16-bit data. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  14-2: Base Timer 
MN706-00002-1v0-E 
462 
MB9Axxx/MB9Bxxx  Series  

 
9. Descriptions of base timer functions 
 
9.3.  Reload timer function 
The function of the base timer can be set to either the 16-bit PWM timer, 16-bit PPG timer, 
16/32-bit reload timer, or 16/32-bit PWC timer using the FMD2, 1, and 0 bits in the Timer 
Control Register. This section explains the timer functions available when the reload timer is 
set. 
1. Operations of the 16-bit reload timer 
2.  Reload timer operation flowchart 
3.  Timer Control Registers (TMCR and TMCR2) and Status Control...

 
9. Descriptions of base timer functions 
 
9.3.1. Operations of the 16-bit reload timer 
In reload timer operations, countdown is performed from the value set in the PWM Cycle Set 
Register in synchronization with the count clock. This operation continues until the count 
value reaches 0 or the cycle setting is loaded automatically to stop the countdown. 
 Count operation performed when th e internal clock is selected 
To start the count operation at the same time counting  is enabled, write 1 to both...