Home > Fujitsu > Controller > Fujitsu Series 3 Manual

Fujitsu Series 3 Manual

Here you can view all the pages of manual Fujitsu Series 3 Manual. The Fujitsu manuals for Controller are available online for free. You can easily download all the documents as PDF.

Page 821

 
5. Registers 
 
5.15.  Comparison Time Setup Register (ADCT) 
The Comparison Time Setup Register (ADCT) sets the comparison time, which is part of the 
A/D conversion time. 
 bit 7 6 5 4 3 2 1 0 
Field Reserved CT2 CT1 CT0 
Attribute  - - -  - - R/W R/W R/W 
Initial value  X X X  X X 1 1 1 
 
[bit 7:3] Reserved: Reserved bits  When writing, always write 0. Wh en reading, 0 is always read. 
 
[bit 2:0] CT2:CT0: Compare clock  frequency division ratio setting bits 
These bits set the division ratio of...

Page 822

 
5. Registers 
 
5.16.  A/D Operation Enable Setup Register (ADCEN) 
The A/D Operation Enable Setup Register (ADCEN) is used to turn the 12-bit A/D converter to 
the operation enable state. 
 bit 7 6 5 4 3 2 1 0 
Field Reserved READY ENBL 
Attribute  - - -  - - - R R/W 
Initial value  X X X  X X X  0 0 
 
[bit 7:2] Reserved: Reserved bits  When writing, always write 0. Wh en reading, 0 is always read. 
 
[bit1] READY : A/D operation enable state bit  This bit indicates whether the A/D converter is in...

Page 823

 
5. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: 12-bit A/D Converter 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  52 
The cycle number of the base clock (HCLK) necessary as  the period of operation enable state transitions 
depends on the CT[2:0] set value of the ADCT register . The cycle number for the set value is as follows: 
ADCT.CT[2:0] Description 
0b000 72 cycles 
0b001 108 cycles 
0b010 144 cycles 
0b011 180 cycles 
0b100 216 cycles 
0b101 252 cycles 
0b110 288 cycles 
0b111 324 cycles 
 
Period...

Page 824

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
788 
MB9Axxx/MB9Bxxx  Series  

Page 825

 
1. Overview 
 
Chapter: A/D Timer Trigger Selection 
This chapter explains the functions and operations to select a timer trigger of the A/D 
converter. 
 
1.
 Overview 
2. Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFBATSB-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-4: A/D Timer  Trigger  Selection 
MN706-00002-1v0-E 
789 
MB9Axxx/MB9Bxxx  Series  

Page 826

 
1. Overview 
 
1. Overview 
This section explains the operations to select a timer trigger of the A/D converter. 
 Selecting a timer trigger of the A/D converter 
The 10-bit A/D converter and th e 12-bit A/D converter are started by the factors shown in Ta b l e  1 - 1 . 
Table 1-1 A/D converter start factor 
Conversion type Start factor 
Priority level 1 conversion    Input from an external trigger pin (at falling edge) 
Priority level 2 conversion  
  Software (when the PCCR:PSTR bit is set to 1)...

Page 827

 
2. Registers 
 
2. Registers 
This section explains the configuration and functions of the registers used to select an A/D 
timer trigger. 
 List of timer trigger selecti on registers for A/D converter 
Abbreviation Register  name See 
SCTSL Scan Conversion Timer Trigger Selection Register  2.1 
PRTSL Priority Conversion Timer Trigger Selection Register  2.2 
 
The functions of the timer trigger selection register s for the A/D converter are common to the 10-bit A/D 
converter and the 12-bit A/D...

Page 828

 
2. Registers 
 
2.1.  Scan Conversion Timer Trigger Selection Register (SCTSL) 
The Scan Conversion Timer Trigger Selection Register (SCTSL) is used to select a timer 
trigger when performing scan conversion. 
 
bit 15 14 13 12 11 10 9 8 
Field Reserved SCTSL[3:0] 
Attribute  R R R  R R/W  R/W  R/W R/W 
Initial value  X X X  X 0 0  0 0 
 
[bit 15:12] Reserved: Reserved bits 
Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 11:8] SCTSL: Scan conversion timer trigger selection bit...

Page 829

 
2. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: A/D Timer Trigger  Selection 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  6 
2.2.  Priority Conversion Timer Trigger Selection Register  (PRTSL) 
The Priority Conversion Timer Trigger Selection Register (PRTSL) is used to select a timer 
trigger when performing priority conversion. 
 
bit 7 6 5 4 3 2 1 0 
Field Reserved PRTSL[3:0] 
Attribute  R R R  R R/W  R/W  R/W R/W 
Initial value  X X X  X 0 0  0 0 
 
[bit 7:4] Reserved: Reserved bits 
Write Has no...

Page 830

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
794 
MB9Axxx/MB9Bxxx  Series  
Start reading Fujitsu Series 3 Manual
All Fujitsu manuals