Fujitsu Series 3 Manual

 
2. UART Interrupt 
 
2.4.  Interrupt and flag set timing when transmit FIFO is used 
When the transmit FIFO is used, an interrupt occurs if the FIFO contains no data. 
 Transmit interrupt and flag set ti ming when transmit FIFO is used 
  If the Transmit FIFO contains no data, the FIFO transmit data request bit (FCR1:FDRQ) is set to 1. 
If FIFO transmit interrupts are enabled (FCR 1:FTIE=1), a transmit interrupt occurs. 
   If a transmit interrupt has occurred and you have  written the required data...

 
3. UART Operation 
 
3. UART Operation 
UART operates in bi-directional serial asynchronous communications in mode 0 and 
master/slave multiprocessor communications in mode 1. 
 UART operation 
  Transmit/receive data format 
  Transmit/receive data always starts w ith a start bit, followed by transmission/reception of data with the 
specified data bit length, and ends wi th at least one-bit long stop bit. 
   The BDS bit of the Serial Mode Re gister (SMR) determines the data transmit direction...

 
3. UART Operation 
 
Figure 3-1 Example transmit/receive data format (operation mode 0/1) 
 
[Operation mode 0]
[Operation mode 1]
ST : Start bit
SP : Stop bit
P : Parity bit
AD : Address bit
D : Data bit
Without P
With PData: 8 bits
ST D0 D1 D2 D3 D4 D5 D6 D7 SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 D7 SP1
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP1
ST D0 D1 D2 D3 D4 D5 D6 SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 SP1
ST D0 D1 D2 D3 D4 D5 D6 P SP1 SP2
ST D0 D1 D2 D3 D4 D5 D6 P SP1 Without P...

 
3. UART Operation 
 
 Data transmission 
  If the transmit data empty flag bit (TDRE) of the Serial Status Register (SSR) is 1, the transmit data 
can be written in the Transmit Data Register (TDR).  (When transmit FIFO is enabled, transmit data can 
be written even if TDRE=0.) 
   If transmit data is written in the Transmit Data Register (TDR), the transmit data empty flag bit 
(SSR:TDRE) is set to 0. 
   Setting the transmission enable bit of the serial contro l register (SCR:TXE) to 1 causes...

 
3. UART Operation 
 
 Data reception 
  When reception is enabled (SCR:RXE=1) , the interface performs reception. 
   Upon detection of the star t bit, one-frame reception takes place acco rding to the data format set in the 
extended communications control register (ESCR:PE N, P, L2, L1, L0) and serial mode register 
(SMR:BDS). A start bit is detected when falling (E SCR:INV=0) is detected after passing the noise 
filter (with the majority value applied after sampling seri al data input three times...

 
3. UART Operation 
 
 Clock selection 
  You can use either an internal or external clock. 
   To use the external clock, set SMR:EXT to 1. IN th is case, the external clock is subject to frequency 
division by the baud rate generator. 
  Start bit detection 
  In asynchronous mode, the start bit is recognized based on detection of the falling edge of the SIN signal. 
For that reason, reception is  not started unless the falling edge of the SIN signal is input even if reception 
is enabled...

 
3. UART Operation 
 
 Parity bit 
  The parity bit can only be added in operation mode 0. The parity enable bit (ESCR:PEN) can be used to 
specify use or non-use of parity and the parity selection bit (ESCR:P) to set even-number parity or 
odd-number parity. 
   Parity cannot be used in operation mode 1. 
Figure 3-2  shows transmit/receive data when parity is enabled. 
Figure 3-2 Operation when parity is enabled 
 
Receive data 
(Mode 0)
Transmit data  (Mode 0)
Transmit data  (Mode 0) ST D0 D1 D2 D4...

 
3. UART Operation 
 
 Hardware flow control 
When flow control is enabled (ESCR:FLWEN=1 ), UART performs hardware flow control. 
   During data transmission 
If 
CTS  is HIGH after data is transmitted, the next  data is not transmitted even if the transmit buffer 
contains data (TDRE=0) and the process waits until 
CTS  is set to LOW. To have transmission 
wait, input HIGH in 
CTS  before the stop bit transmission is completed. Transmission continues up 
to the stop bit even if HIGH is input in 
CTS...

 
3. UART Operation 
 
  If FIFO is used 
If SSR:RDRF is not set (the specified number of  data sets are not received in receive FIFO), 
RTS 
outputs HIGH upon reception of data one bit before the stop bit, but 
RTS outputs LOW upon 
detection of the stop bit. (For period 1) 
If SSR:RDRF is set (the specified number of  data sets are received in receive FIFO), 
RTS outputs 
HIGH upon reception of data one  bit before the stop bit. 
RTS  outputs LOW after all data is 
read from receive FIFO. (For period...

 
4. Dedicated Baud Rate Generator 
 
4.  Dedicated Baud Rate Generator 
For the UART transmit/receive clock source, either of the following can be selected. 
- Dedicated baud rate generator (reload counter) 
- An external clock input to the baud rate generator (reload counter) 
 Selecting the UART baud rate 
Select one of the following two baud rates. 
  Baud rate obtained by dividing an internal clock using the dedicated baud 
rate generator (reload counter) 
This generator provides two internal...