Fujitsu Series 3 Manual
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Page 901
3. CSIO (Clock Sync Serial Interface) operations Continuous data transmit or receive waiting If anything other than (ESCR:WT1, ESCR.WT0)=(0, 0) is set for the continuous data transmission or reception, a wait is inserted between frames. - ESCR.WT1=0, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte1bit - ESCR.WT1=1, ESCR.WT0=0 (in master mode operation) SCK 1Byte 2Byte2bit - ESCR.WT1=1, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte3bit TDRE TDRE TDRE FUJITSU SEMICO NDUCTOR...
Page 902
3. CSIO (Clock Sync Serial Interface) operations Slave mode operation (Set SCR:MS=1 and SMR:SCKE=0.) Data transmission 1. If serial data output is enabled (SMR:SOE=1) and data transmission is enabled (SCR:TXE=1) and when the transmit data is written in the TD R, the SSR:TDRE bit is set to 0. This causes the transmit data to be output in synchronization with a falling edge of the serial clock (SCK) input. 2. When the transmit data of the first bit is output, the SSR:TDRE bit is set to...
Page 903
3. CSIO (Clock Sync Serial Interface) operations 3.2. Normal transfer (II) Features Item Description 1 Serial clock (SCK) signal detect level LOW 2 Transmit data output timing SCK signal rising edge 3 Receive data sampling SCK signal falling edge 4 Data length 5 to 9 bits Register settings The register values required for normal data transfer (II) are listed on the table below. Table 3-2 Normal transfer (II) register settings Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit...
Page 904
3. CSIO (Clock Sync Serial Interface) operations Normal transfer (II) timing chart Data transmission SCK SOUT TDR RW TXE Data reception SIN RXE Sampling RDRF TDRE Signal detect level RDR RD D 7 D0 D 7 D 1 D2 D3 D 4 D5 D6 D0 D1 D2D3 D4 D5 D6 D7 D0 D7 D 1 D 2 D3 D 4 D5 D6 D0 D1 D2 D3 D4 D5 D6 1st byte 2nd byte * A D7 val ue if SCR:MS=1 HIGH if SCR:MS=0 * A : FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E...
Page 905
3. CSIO (Clock Sync Serial Interface) operations Master mode operation (Set SCR:MS=0 and SMR:SCKE=1.) Data transmission 1. If serial data output is enabled (SMR:SOE=1), da ta transmission is enabled (SCR:TXE=1) and data reception is disabled (SCR:RXE=0), and when the transmit data is written in the TDR, the SSR:TDRE bit is set to 0. This causes the transmit data to be output in synchronization with a rising edge of the serial clock (SCK) output. 2. When the transmit data of the...
Page 906
3. CSIO (Clock Sync Serial Interface) operations Continuous data transmit or receive waiting If anything other than (ESCR:WT1, ESCR.WT0)=(0, 0) is set for the continuous data transmission or reception, a wait is inserted between frames. - ESCR.WT1=0, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte1bit - ESCR.WT1=1, ESCR.WT0=0 (in master mode operation) SCK 1Byte 2Byte2bit - ESCR.WT1=1, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte3bit TDRE TDRE TDRE FUJITSU SEMICO NDUCTOR...
Page 907
3. CSIO (Clock Sync Serial Interface) operations Slave mode operation (Set SCR:MS=1 and SMR:SCKE=0.) Data transmission 1. If serial data output is enabled (SMR:SOE=1) and data transmission is enabled (SCR:TXE=1) and when the transmit data is written in the TD R, the SSR:TDRE bit is set to 0. This causes the transmit data to be output in synchronization with a rising edge of the serial clock (SCK) input. 2. When the transmit data of the first bit is output, the SSR:TDRE bit is set to...
Page 908
3. CSIO (Clock Sync Serial Interface) operations 3.3. SPI transfer (I) Features Item Description 1 Serial clock (SCK) signal detect level HIGH 2 Transmit data output timing SCK signal rising edge 3 Receive data sampling SCK signal falling edge 4 Data length 5 to 9 bits Register settings The register values required for SPI data transfer (I) are listed on the table below. Table 3-3 SPI transfer (I) register settings Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 09 Bit 08...
Page 909
3. CSIO (Clock Sync Serial Interface) operations SPI transfer (I) timing chart *B Data transmission 1st byte 2nd byte *A D7 D0D7 D1D2 D3D4 D5D6D0 D1D2D3D4 D5 D6 D7 D0 D7 D1D2 D3 D4 D5D6 D0D1D2D3 D4 D5D6 SOUT SC K TDRE TDR RW TXE Data reception SIN Sampling RDRF RDR RD RXE * A : During slave mode transmission(MS=1, SOE=1), 4 machine cycles or more time is required after writing data in the TDR . * B : HIGH if SCR:MS=0 D0 of the 3rd byte if SCR:MS=1 and TDRE is LOW...
Page 910
3. CSIO (Clock Sync Serial Interface) operations Master mode operation (Set SCR:MS=0 and SMR:SCKE=1.) Data transmission 1. If serial data output is enabled (SMR:SOE=1), da ta transmission is enabled (SCR:TXE=1) and data reception is disabled (SCR:RXE=0), and when the transmit data is written in the TDR, the SSR:TDRE bit is set to 0. This causes the first bit to output. Then, the transmit data is output in synchronization with a rising edge of the serial clock (SCK) output. 2. The...
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