Fujitsu Series 3 Manual

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 10] RDRF: Receive data full flag bit 
  This flag shows the state of  Receive Data Register (RDR). 
   When the receive data is loaded in  the RDR, this bit is set to 1. When data is read from the Receive 
Data Register (RDR), this bit is cleared to 0. 
   If the RDRF bit and SCR:RIE  bit are 1, a receive interrupt request is output. 
   If receive FIFO is used and if the preset amount of data is received in  receive FIFO, the RDRF bit is set...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.4.  Extended Communication Control Register (ESCR) 
The Extended Communication Control Register (ESCR) is used to set a transmit/receive data 
length and to fix the serial data output to the HIGH state. 
 
Bit 15 ... 8 7 6 5 4 3 2 1 0 
Field - SOP - - WT1 WT0 L2 L1 L0 
Attribute     R/W  - - R/W R/W R/W  R/W R/W 
Initial 
value     0 - - 0 0 0 0 0 
 
[bit 7] SOP: Serial output pin set bit    This bit sets the serial data output pin to the HIGH st...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 4:3] WT1, WT0: Data transmit/receive wait select bits 
In master operation mode, these bits set a wait count fo r continuous data transmission or reception. In slave 
operation mode, these bits are set to 00. 
   If set to 00: The SCK clocks are output continuously. 
   If set to 01: The SCK clock is output after waiting for a single-bit time. 
   If set to 10: The SCK clock is output after waiting for a two-bit time. 
   If set to 11: The SCK...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.5.  Receive Data Register/Transmit Data Register 
(RDR/TDR) 
The Receive and Transmit Data Registers are allocated at the same address. This register 
functions as the Receive Data Register when data is read from it. This register operates as 
the Transmit Data Register when data is written in it. 
 Receive Data Register (RDR) 
 
Bit 15 ... 98 7 6 5 4 3 2 1 0 
Field  D8 D7 D6 D5 D4 D3 D2 D1 D0 
Attribute      R R R R R  R R R R 
Initial 
value     0...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
  Transmit Data Register (TDR) 
 
Bit 15 ... 98 7 6 5 4 3 2 1 0 
Field  D8 D7 D6 D5 D4 D3 D2 D1 D0 
Attribute      W W W W W  W W W W 
Initial 
value     1 1 1 1 1 1 1 1 1 
 
The Transmit Data Register (TDR) is a 9-bit data buffer register for serial data transmission. 
   If data transmission is enabled (SCR:TXE=1) and if the transmit data is written in the Transmit Data 
Register (TDR), the transmit data is transferred to the transmit shift...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.6.  Baud Rate Generator Registers 1 and 0 (BGR1 and 
BGR0) 
Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency 
division ratio of serial clocks. 
 
Bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field - (BGR1) (BGR0) 
Attribute  - R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W  R/W R/W R/WR/W
Initial 
value  - 
0 0 0 0 0 0  0 0 0  0 0 0 0 0 0 
 
   These bits set a clock frequency division in Baud Rate Generator Registers 1 and 0...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
 
  Data must be written in the Baud Rate Generator  Registers (BGR1 and BG
 R0) by 16-bit data accessing. 
   If the reload value is even, the HIGH and LOW width of serial clock are as follows. If the value is 
odd, the serial clock has the same HIGH and LOW signal width. 
If SMR:SCINV=0, the HIGH width of serial clock is longer for 1 cycle of bus clock. 
If SMR:SCINV=1, the LOW width of serial clock is longer for 1 cycle of bus clock. 
   Set the...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.7.  FIFO Control Register 1 (FCR1) 
The FIFO Control Register (FCR1) is used to set the FIFO test, select the transmit or receive 
FIFO, enable the transmit FIFO interrupt, and control the interrupt flag. 
 
Bit 15 14 13 12 11 10 9 8 7 ... 0 
Field FTST1 FTST0 - FLSTEFRIIEFDRQFTIE FSEL (FCR0) 
Attribute  R/W R/W  - R/W R/W  R/W R/W R/W    
Initial 
value  0 0 - 0 0 1 0 0    
 
[bit 15:14] FTST1, FTST0: FIFO test bits  They are FIFO Test bits. 
They...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 11] FRIIE: Receive FIFO idle detection enable bit 
This bit sets to detect the receive id le state if the receive FIFO contains  valid data and if it continues more 
than 8-bit hours. If the r eceive interrupt is enabled (SCR:RIE=1), a  receive interrupt is generated when the 
receive idle state is detected. 
If set to 0: The receive idle  state detection is disabled. 
If set to 1: The receive idle state detection is enabled. 
Bit Description 
0...

 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 9] FTIE: Transmit FIFO interrupt enable bit 
This bit enables a transmit FIFO interrupt. If this bit is  set to 1, an interrupt occurs when the FDRQ bit is 
set to 1. 
Bit Description 
0  Disables the transmit FIFO interrupt. 
1  Enables the transmit FIFO interrupt. 
 
[bit 8] FSEL: FIFO select bit  This bit selects the tr ansmit or receive FIFO. 
If set to 0: Set the transmit FIFO as  FIFO1, and the receive FIFO as FIFO2. 
If set to 1: Set the...