Fujitsu Series 3 Manual

 FUJITSU SEMICONDUCTOR LIMITED 
5.  Operation Mode 3 (LIN Communication Mode) Setting Procedure and Program Flow 
In Operation Mode 3 (LIN communication mode), the LIN interface (Ver. 2.1) can be used for a 
LIN master or LIN slave system. 
 Register settings 
  CPU-to-CPU connection 
Figure 5-1  shows a communication system consisting of  one LIN master and one LIN sl ave. The LIN 
interface (ver. 2.1) can work as  a LIN master or a LIN slave. 
Figure 5-1 An example of LIN bus system communication...

 FUJITSU SEMICONDUCTOR LIMITED 
 Example flowchart 
  Master mode operations 
Figure 5-2 An example flowchart of LIN communication in master mode (when FIFO is not used) 
Start
Initial settings:
Set the operation mode to 3 and master mode.
Enable the serial data output, and set a baud rate.
Set an LIN Break length and a Break delimiter length.
TXE=1, TIE=0, RXE=1, RIE=1
Message?
Yes NoWake up ?
Yes
No
LIN Break field transmission: LBR=1
LIN Sync field transmission: TDR=0x55
RDRF=1
Receive interrupt
LIN...

 FUJITSU SEMICONDUCTOR LIMITED 
Figure 5-3 An example flowchart of LIN comm unication in master mode (when FIFO is used) 
Start
Initial settings:
Set the operation mode to 3 and master mode.
Enable the serial data output, and set a baud rate.
Set an LIN Break length and a Break delimiter length.
TXE=1, TIE=0, RXE=1, RIE=1
FSEL=0, FE1=1,FE2=0, FTIE=0
Message?
YesNoWake up ?
Yes
No
LIN Break field transmission: LBR=1
Write N bytes in TDR.
RDRF=1
Receive interrupt
Receive Data1.*1
Error existing?
Error...

 FUJITSU SEMICONDUCTOR LIMITED 
 Slave mode operations 
Figure 5-4 An example flowchart of LIN communica tion in slave mode (when FIFO is not used) 
Start
Initial settings:
Set the operation mode to 3 and 
master mode.
TXE=1,TIE=0,RXE=0,RIE=1
Connect between UART and ICU.
RXE=0, enable ICU interrupt.
LBIE=1
LBD=1
Sync Break interrupt
LBD=0, LBIE=0
Enable ICU interrupt.
ICU interrupt
Read the ICU data.
Clear the ICU interrupt flag.
ICU interrupt
Read the ICU data.
Adjust the baud rate.
RXE=1
Clear the...

 FUJITSU SEMICONDUCTOR LIMITED 
Figure 5-5 An example flowchart of LIN comm unication in slave mode (when FIFO is used) 
Start
Initial settings:
Set the operation mode to 3 and 
master mode.
TXE=1,TIE=0,RXE=0,RIE=1
FE1=1, FE2=0, FSEL=0
Connect between UART and ICU.
RXE=0, enable ICU interrupt.
LBIE=1
LBD=1
Sync Break interrupt
LBD=0, LBIE=0
Enable ICU interrupt.
ICU interrupt
Read the ICU data.
Clear the ICU interrupt flag.
ICU interrupt
Read the ICU data.
Adjust the baud rate. RXE=1
Clear the ICU...

 
6. LIN Interface (ver. 2.1) Registers 
 
6.  LIN Interface (ver. 2.1) Registers 
The following shows a list of LIN interface (ver. 2.1) registers. 
  List of LIN interface  (ver. 2.1) registers 
Table 6-1 List of LIN interface (ver. 2.1) registers 
  bit 15                       bit 8  bit 7                        bit 0 
SCR (Serial Control Register)  SMR (Serial Mode Register) 
SSR (Serial Status Register) ESCR (Extended Communication Control Register)
- RDR/TDR (Transmit/Receive Data Register) 
BGR1...

 
6. LIN Interface (ver. 2.1) Registers 
 
6.1.  Serial Control Register (SCR) 
The Serial Control Register (SCR) is used to  enable/disable a transmit/receive interrupt, 
enable/disable a transmit idle interrupt, and enable/disable data transmission and reception. 
Also, the SCR can be used to generate an LIN Break field and reset the LIN interface (ver. 
2.1). 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field UPCL MS LBR RIE TIE TBIE RXE TXE (SMR) 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W    
Initial...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 14] MS: Master/Slave function select bit 
Selects the master or slave mode. 
If set to 0: The master mode is selected. 
If set to 1: The slave mode is selected. 
Bit Description 
0 Master  mode 
1 Slave mode 
 
[bit 13] LBR: LIN Break Field setting bit (valid in master mode only)  If this bit is set to 1, an LIN Break field (having the length set by the ESCR:LBL1/0 bit) is generated. 
Also, an LIN Break delimiter (set by  the ESCR:DEL1/0 bit) is generated....

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 11] TIE: Transmit interrupt enable bit 
  This bit enables or disables an output  of transmit interrupt request to the CPU. 
   If the TIE and SSR:TDRE bits are 1, a  transmit interrupt request is output. 
 
Bit Description 
0  Disables a transmit interrupt. 
1  Enables a transmit interrupt. 
 
[bit 10] TBIE: Transmit bus idle interrupt enable bit    This bit enables or disables an output of tr ansmit bus idle interrupt request to the CPU. 
   If the...

 
6. LIN Interface (ver. 2.1) Registers 
 
[bit 8] TXE: Data transmission enable bit 
This bit enables or disables a data tran smission by the LIN interface (ver. 2.1). 
   If set to 0: The data frame transmission is disabled. 
   If set to 1: The data frame transmission is enabled. 
 
Bit Description 
0  Disables the transmission. 
1  Enables the transmission. 
 
 
If dat a

 transmission is disabled (TXE=0), the current data transmission is stopped immediately. 
  
FUJITSU SEMICONDUCTOR LIMITED...