Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
 Acknowledgement reception by first byte transmission 
When the data direction bit (R/W) is output, the I2C interface receives acknowledgement from a slave. The 
following lists operations to enable/disable FIFO. 
Table 2-2 Operations after acknowledgement reception with DMA mode disabled  (IBSR:RSA bit=0, SSR:DMA bit=0) 
Operation immediately after receiving acknowledgement Transmit 
FIFO  Receive 
FIFO  Transmit 
FIFO 
status Receive 
FIFO 
status  Data 
direction  bit...

FUJITSU SEMICONDUCTOR LIMITED 
Table 2-3 Operations after acknowledgement reception with DMA mode enabled (IBSR:RSA bit=0, SSR:DMA bit=1) 
Operation immediately after receiving acknowledgement Transmit 
FIFO  Receive 
FIFO  Transmit 
FIFO 
status Receive 
FIFO 
status  Data 
direction  bit 
(R/W) Acknowledgement: ACK 
Acknowledgement: 
NACK 
0 
Disable Disable  - - 
1 If the SSR:TDRE bit is set to 1, the 
interface sets the SSR:TBI bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
SSR:TBI bit stays...

FUJITSU SEMICONDUCTOR LIMITED 
To enable FIFO   Before setting 1 to the IBCR:MSS bit, it is needed to set the following for FIFO. 
   When transmitting to a slave (the data direction bit=0), data including the slave address must be set 
to transmit FIFO. 
   When receiving data from a slave (the data direction  bit=1), the FIFO Byte Register must be set with 
the number of data sets to be received, and  dummy data must be written to the Transmit Data 
Register for the slave address, data direction bit...

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Figure 2-7 Acknowledgement   (when FIFO is disabled, IBSR:RSA=0, and ACK response is selected) 
                            Set to L by INT bit.                         Data 
SCL                                                                
SDA                  R/W           ACK                           
                                                Set to 0. 
INT bit 
 
RACK bit 
 
FBT  bit  
 
TDRE bit 
Write in the TDR register.
 
The following describes the wait...

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Figure 2-9 Acknowledgement   (when FIFO is disabled, IBSR:RSA=1, and ACK response is selected) 
                            Set to L by INT bit.                     Data 
SCL                                                                
SDA                   R/W                        ACK                          
                                               Set to 0. 
IN T bi t 
 
RA CK  bi t 
 
FB T b it  
 
RS A bit  
 
RD RF  bit  
The RDR  register is read....

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Figure 2-11 Acknowledgement (when FIFO is enabled, transmit FIFO has data, receive FIFO 
has no data, IBSR:RSA=0, and ACK response is selected) 
                                                         Data 
SCL                                                               
SDA                   R/W          ACK                         
                                                
IN T bit   
RA CK  bit  
 
FB T b it  
  TDRE bit 
 
 
 Data transmission by the master...

FUJITSU SEMICONDUCTOR LIMITED 
Table 2-5 IBCR:WSEL bit status for master data transmission when DMA mode is enabled (SSR:DMA=1) 
WSEL bit Operation 
0   
After the second byte, after acknowledgement with 1 set for 
the SSR:TDRE bit, the transmit 
bus idle flag (SSR:TBI) is set to 1 and SCL  to LOW for the wait state after acknowledgement 
with 1 set for the SSR:TDRE bit. 
 
Starts the wait state by setting the transmit bus idle flag (SSR:TBI) to 1 after acknowledgment 
when no more valid data remain in...

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2. To transmit data to a reserved address: 

 When transmit FIFO is disabled: 
1.
 Sets the reserved address for Sl ave Address in the TDR register and writes 1 to the IBCR:MSS 
bit. 
2.
 After the Slave Address setting is transmitted, th e interrupt flag (IBCR:INT) is set to 1. 
3.
 Reads from the RDR register and c onfirms the reserved address.(*1) 
4.
 Writes transmit data to the TDR register. 
5.
 Writes 0 to the interrupt flag (IBCR:INT) upon updating of the IBCR:WSEL...

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 When transmit FIFO is enabled: 
1.
 Writes an address for Slave Address (including the  data direction bit) and transmit data to the TDR 
register.  
2.
 Writes 1 to the IBCR:MSS bit upon setting of the IBCR:WSEL bit. 
3.
 If NACK is received during transmission, sets  the interrupt flag (IBCR:INT) to 1 immediately 
after that to put the I2C bus in the wait state. If ACK responses  are received for all bytes, sets the 
transmit bus idle flag (SSR:TBI) to 1 according to...

FUJITSU SEMICONDUCTOR LIMITED 
 When transmit FIFO is enabled: 
1.
 Sets the reserved address for Sl ave Address in the TDR register and writes 1 to the IBCR:MSS 
bit.  
2.
 After the Slave Address setting is transmitted, th e interrupt flag (IBCR:INT) is set to 1. 
3.
 Reads from the RDR register and c onfirms the reserved address.(*1) 
4.
 Writes all transmit data to the TDR register (un til transmit FIFO becomes full if it is the case). 
5.
 If NACK is received during transmission, sets  the...