Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-12 Master mode interrupt 1 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=0) 
 
  
Slave Address S WACK DataACKDataACKDataACK P or Sr
 
  




S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is written in the TDR register, and...

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-14 Master mode transmit interrupt 3 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0, NACK response) 
 
  
Slave Address S WACK DataACKDataACKDataNACKP or Sr
 
 



 
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is...

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-16 Master mode transmit interrupt 5 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=1 -> 0, IBSR:RSA=0, ACK response) 
 
 
 
Slave Address S WACK DataACKDataACKDataACK P or Sr
 
  




S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is...

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-18 Master mode transmit interrupt 7 by enabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=0, ACK response) 
 
 
 
 
  
P or SrACK Data ACK
DataACK
DataACK W
S Slave Address 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if the Send FIFO buffer is emptied.   
- The send data is written in the Send FIFO buffer, and INT bit is set to 0....

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-20 Master mode transmit interrupt 9 by enabling FIFO   (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0, NACK response) 
 
  


P or SrNACK Data ACK
DataACK
DataACK W
S Slave Address
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if the Send FIFO buffer is emptied.   
- The send data is written in the Send FIFO buffer, and INT bit is set to 0....

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-22 Master mode transmit interrupt 11 by disabling FIFO   (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0, ACK response) 
 
  
 
 
 
 




P or SrACK DataACK
DataACK
DataACK W
S Slave Address 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- The send data is...

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-24 Master mode transmit interrupt 13 by disabling FIFO (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0, NACK response during transmission) 
 
  
  



P or SrNACK DataACK
DataACK
DataACK W
S Slave Address 
 
  
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent,...

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-26 Master mode interrupt 15 by disabling FIFO   (SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=1) 
 
  
S ACK ACK Slave Address WDataACKDataACKData P or Sr
 
 
Figure 2-27 Master mode transmit interrupt 16 by enabling FIFO   
(SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=0, ACK response) 
 
 
 
 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt...

FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-28 Master mode transmit interrupt 17 by enabling FIFO   (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) 
 
  
S ACK ACK W DataACKDataACKData P or SrSlave Ad
dress
  

 
S: Start condition 
W: Data direction bit (writing) 
P: Stop condition 
Sr: Iteration start condition 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs if the Send FIFO buffer is emptied. 
- The send data is written in the Send FIFO buffer. 
 An interrupt...

FUJITSU SEMICONDUCTOR LIMITED 
   Data reception by the master 

 When DMA mode is disabled (SSR:DMA=0) 
When the data direction bit (R/W) is set to 1, the master receives data transmitted from a slave.   
When FIFO is disabled, the master operates as follows. 

 If the SSR:TDRE bit is set to 1, wait is generated (IBCR:INT=1, SSR:RDRF=1) each time one 
byte is received . At this time, an ACK or NACK re sponse is returned, according to the setting of the 
ACKE bit in the IBCR register, be fore wait if...