Fujitsu Series 3 Manual

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[bit 12] WSEL: Wait selection bit 
 If DMA mode is disabled (SSR:DMA=0), this bit selects a generation time of interrupt before or after 
acknowledgement (INT=1) an d selects to wait the I2C bus or not. 

 If DMA mode is enabled (SSR:DMA=1), this bit sel ects a generation time of interrupt before or after 
acknowledgement (INT=1,  and SSR:TBI=1 for transmission or SSR:RDRF=1 for reception) and 
selects to wait the I
2C bus or not. 

 The WSEL bit is invalid in the...

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[bit 9] BER: Bus error flag bit 
This bit indicates that an error has been detected on the I2C bus. 
The BER bit is set when:  1.
 The start or stop condition is detected during transmission of the first byte. (*1) 
2.
 The (iteration) start condition or the stop condition is  detected at bit 2 to 9 (acknowledgement) of data 
after the 2nd or subsequent byte. 
 
The BER bit is reset when: 
1.
 The INT bit is set to 0 if BER=1. 
2.
 The I2C interface operation is disabled...

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  1.
 An arbitration lost is detected in the first byte. 
2.
 The NACK signal is received during the time othe r than stop condition output setting (the MSS bit 
is set to 0 during the master mode operation). 
3.
 The WSEL bit is 0 and an arbitration lost is detected in the 2nd or subsequent byte. 
4.
 The reserved address is not detected in the 1st byte, and data is fo und in the receive FIFO when the 
receive FIFO is enabled and data is received in master or slave mode...

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The INT bit is reset when: 1.
 The INT bit is set to 0. 
2.
 The INT bit is 1 and the ACT bit is 1, the MSS bit is set to 0. 
3.
 The INT bit is 1 and the ACT bit is 1, the SCC bit is set to 1. 
 
If the DMA mode is disabled (SSR:DMA=0), it is invalid to set the INT bit to 1. 
Description Bit  During writing During reading 
0  Clears the INT bit.  Does not issue an interrupt request. 
1  No effect  Issues an interrupt request. 
 
 

 When DMA mode is enabled (SSR:DMA=1)...

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5.2.  Serial Mode Register (SMR) 
The Serial Mode Register (SMR) is used to set an operation mode, and to enable or disable 
the transmit/receive interrupt. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SCR) MD2 MD1 MD0 WUCRRIE TIE ITST1 ITST0
Attribute     R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7:5] MD2, MD1, MD0: operation mode set bits 
These bits set an operation mode. 
0b000: Sets operation mode 0 (async normal mode). 
0b001: Sets...

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[bit 3] RIE: Receive interrupt enable bit 
 This bit enables or disables an output of receive interrupt request to the CPU. 

 If the RIE bit and the receive data flag bit (SSR:RDRF) are 1, or if any of erro r flag bits (SSR:ORE) is 
1, a receive interrupt request is output. 
 
Bit Description 
0  Disables the receive interrupt. 
1  Enables the receive interrupt. 
 
 
To recei ve 

data using the INT bit of I
2C Bus Control Register (IBCR) when DMA mode is disabled...

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5.3. I2C Bus Status Register (IBSR) 
The I2C Bus Status Register (IBSR) shows the iteration start, acknowledgement, data 
direction, arbitration lost, stop condition, I2C bus status, and bus error detection. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SSR) FBT RACKRSA TRX AL RSC SPC BB 
Attribute      R R R  R R R/W R/W  R 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] FBT: First byte bit 
This bit indicates the first byte. 
The FBT bit is set when: 
1.
 The (iteration) start...

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[bit 5] RSA: Reserved address detection bit 
This bit shows that the reserved address has been detected. 
The RSA bit is set (RSA=1) when:  1.
 The 1st byte is 0000xxxx or 1111xxxx. where, x can be 0 or 1. 
 
The RSA bit is reset (RSA=0) when: 
1.
 The (iteration) start condition is detected. 
2.
 The stop condition is detected. 
3.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
4.
 A bus error is detected (IBCR:BER bit=1). 
 
If the RSA bit is set to 1 in the...

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[bit 4] TRX: Data direction bit 
This bit indicates the data transmission direction. 
The TRX bit is set when: 1.
 The (iteration) start condition is sent in master mode. 
2.
 Bit 8 of the 1st byte is 1 in slave mode (in the slave mode transmission direction). 
 
The TRX bit is reset when: 
1.
 An arbitration lost occurs (AL=1). 
2.
 Bit 8 of the 1st byte is 0 in slave m ode (in the slave mode reception direction). 
3.
 Bit 8 of the 1st byte is 1 in master mode  (in the...

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[bit 2] RSC: Iteration start condition check bit 
This bit shows that an iteration start condition is detected in master or slave mode. 
The RSC bit is set when: 1.
 When an iteration start condition is detected after acknowledgement, during the master or slave mode operation. 
 
The RSC bit is reset when: 
1.
 The RSC bit is set to 0. 
2.
 The IBCR:MSS bit is set to 1. 
3.
 The I2C interface operation is disabled (ISMK:EN bit=0). 
 
It is invalid to set this bit to 1. 
Bit...