Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
 When transmit/receive FIFO is enabled: 
1.
 Sets the number of bytes to be received to the FBYTE register. 
2.
 Writes an address for Slave Address (including the data direction bit) and dummy data in the number  of bytes to be received  to the TDR register.   
3.
 Writes 1 to the IBCR:MSS bit. 
4.
 An ACK response is returned and data reception co ntinues as long as the SSR:TDRE bit stays 0. 
During that reception operation, SSR:RDRF is set to 1 when the number of bytes...

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 When receive FIFO is disabled: 
1.
 Sets Slave Address (including the data direction  bit) to the TDR register and writes 1 to the 
IBCR:MSS bit.   
2.
 ACK is received after the Slave Ad dress setting is transmitted, and then the transmit bus idle flag 
(SSR:TBI) is set to 1. 
3.
 Writes data to be transmitted to the TDR re gister to release the wait state of the I2C bus. 
4.
 After one byte is received, sets the transmit bus id le flag (SSR:TBI) and the receive data...

FUJITSU SEMICONDUCTOR LIMITED 
 
 When seven-bit slave address detection is enabled (ISBA:SAEN=1), it is prohibited to specify a 
seven-bit slave address in master mode. 

 When SSR:TDRE is 0, even if an overrun error occurs, acknowledgement is output according to the 
setting for the IBCR:ACKE bit, and then the next process should follow.   

 To change the IBCR register during transmission/reception, do so when the interrupt flag (IBCR:INT) is 
1 or when the transmit bus idle flag (SSR:TBI) is 1...

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Figure 2-30 Master mode receive interrupt 1 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=0) 
 
 
S R ACK Data DataACKDataACK P or SrSlave AddressNACK 
 


 

 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.  - If the INT bit is set to 0, the interrupt flag is cleared to 0. 
 An interrupt occurs when a single byte is received and an ACK is sent. 
-...

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Figure 2-32 Master mode receive interrupt 3 by enabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBCR:ACKE=0, IBSR:RSA=0) 
 
 
S R ACK Data Slave Address DataACKDataACK P or SrNACK 
 
 

 
 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if TDRE bit is set to 1. 
- The entire data is read from the Receive FIFO buffer
, and MSS bit is set to 0 or both MSS   
and SCC bits are set to 1.
 
 
Figure 2-33 Master mode receive interrupt 4 by enabling FIFO...

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Figure 2-35 Master mode receive interrupt 6 by disabling FIFO   (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) 
 
 
S R ACK Data Slave Address DataACKDataACK P or SrNACK 
 
 
  

  
 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received. 
- Dummy data is written in the TDR register. 
 An interrupt occurs when a single byte is received. 
- After the...

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 Arbitration lost 
If the master receives the data different from sent data, due to concurrent transmission of data from another 
master, the master judges the situation as arbitration lost. At this time, the IBCR:MSS bit is set to 0 and 
the IBSR:AL bit to 1, enabling operation in slave mode.   
The IBSR:AL bit can be cleared to 0 under the following conditions: 

 The IBCR:MSS bit is set to 1. 

 The IBCR:INT bit is set to 0. 

 The IBSR:SPC bit is set to 0 when the...

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 Issuing iteration start condition when DMA mode  is enabled (SSM:DMA=1) 
When writing a slave address to the TDR register wh ile the transmit bus is idle (SSR:TBI=1) and the 
interrupt flag (IBCR:INT) is 0, transmission star ts and the iteration start condition cannot be issued. 
Therefore, to issue the iteration start condition while  the transmit bus is idle (SSR:TBI=1) and the 
interrupt flag (IBCR:INT) is 0, follow the steps below. 
1.
 Set the IBCR:INT bit to 1. At...

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2.3. Slave mode 
If the (iteration) start condition is detected and a combination of the ISBA and ISMK registers 
matches the received address, the interface outputs an ACK response and acts in slave 
mode. 
 Slave address match detection 
After the (iteration) start condition is detected, subsequent seven bits are received as the address. For each 
of the bits that are set to 1 in the ISMK register, the ISBA register is compared with the received address. 
If they match,...

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 Data direction bit 
After receiving the address, the interface receives the data direction bit to determine whether to transmit or 
receive data. If this bit is 0, it  means that data is transmitted from  the master device, and the interface 
receives data as a slave device. 
 Reception in slave mode 
If the received data matches the slave address and the data  direction bit is 0, it means that data is received 
in slave mode. The following  shows a procedure example to...