Fujitsu Series 3 Manual

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 When receive FIFO is enabled: 
1.
 If NACK is detected, the interrupt flag  (IBCR:INT) is set to 1, and the I2C bus is placed into the 
wait state. When receive FI FO becomes full, place the I2C bus into the wait state. If the stop or 
iteration start condition is detected, the IBSR:SPC and IBSR:RSC bits are set to 1, and the interrupt 
flag (IBCR:INT) is not set to 1 (the I
2C bus is not placed into the wait state). Receive FIFO sets the 
SSR:RDRF bit to 1 when the set...

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Figure 2-41 Slave mode receive interrupt 3 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0) 
 
 
S Slave Address ACK Data W DataACKDataACK P or SrNACK
    

   

 
 
Figure 2-42 Slave mode receive interr upt 4 by enabling receive FIFO   
(SSR:DMA=0, IBSR:RSA=0) 
 
  
 
Figure 2-43 Slave mode receive interr upt 5 by enabling receive FIFO   
(SSR:DMA=0, IBSR:RSA=0) 
 
  
 
   : Interrupt by INTE =1  
  : Interrupt by CNDE = 1  
As the slave address...

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Figure 2-44 Slave mode receive interrupt 6 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=1) 
 
 
S Slave Address ACK Data ACK W DataACKDataACK P or Sr
  
 

 
 
Figure 2-45 Slave mode receive interrupt 7 by disabling FIFO   
(SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=0) 
 
  
 
   : Interrupt by INTE =1 
  : Interrupt by CNDE = 1  
  : Interrupt by  RIE =1 
 As the slave address matches , an ACK is output and an interrupt is generated .
-
ACKE bit is set to  1...

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Figure 2-46 Slave mode receive interrupt 8 by disabling FIFO   (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) 
 
 
S ACK Data ACK W DataACKDataACK P or SrSlave Address
  
  
 
 
Figure 2-47 Slave mode receive interrupt 9 by disabling FIFO   
(SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) 
 
  
 
   : Interrupt by INTE= 1  
  : Interrupt by CNDE= 1  
  : Interrupt by  RIE =1
As the slave address matches  , an ACK is output and an interrupt is generated .
-
 ACKE bit is set to  1...

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Figure 2-48 Slave mode receive interrupt 10 by enabling receive FIFO   
(SSR:DMA=1, IBSR:RSA=0) 
 
 
S ACK Data ACK W DataACKDataACK P or SrSlave Address
 

 
 
Figure 2-49 Slave mode receive interrupt 11 by enabling receive FIFO   
(SSR:DMA=1, IBSR:RSA=0) 
 
  
 
Figure 2-50 Slave mode receive interrupt 12 by disabling FIFO   (SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=1) 
 
  
 
   : Interrupt by INTE =1 
  : Interrupt by CNDE = 1  
An interrupt occurs when the stop condition...

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 Transmission in slave mode 
If the received data matches the slave address and the data direction bit is 1, it means that data is 
transmitted in slave mode. If FIFO is disabled, set  the interrupt flag (IBCR:INT) to 1 after transmitting 
one byte or outputting an acknowledgement response  depending on setting of the IBCR:WSEL bit. Then 
place the I
2C bus into the wait state (see  Ta b l e  2 - 8). 
Using the IB
SR:RACK bit, check the acknowledgement output from the...

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2.4. Bus error 
If the stop or (iteration) start condition is detected while transmitting or receiving data on the 
I2C bus, it is handled as a bus error. 
 Bus error occurrence condition 
If a bus error occurs, the IBCR:BER bit is set to 1 in the following conditions. 

 The (iteration) start or stop condition is detected while transferring the first byte. 

 The (iteration) start condition or stop condition is de tected at bit 2 to 9 (acknowledgement) of data. 
 Bus...

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3.  Dedicated Baud Rate Generator 
The dedicated baud rate generator configures the setting of the serial clock frequency. 
 Selecting the baud rate 

 Baud rate obtained by dividing an internal clock using the dedicated baud 
rate generator (reload counter) 
This generator provides two internal reload counters, which support transmitting and receiving serial clocks 
respectively. To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers...

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 Reload values and baud rates for each bus clock frequency 
Table 3-1 Reload values and baud rates 8 MHz 10 MHz 16 MHz 20 MHz 24 MHz 32MHz 
Baud rate [bps]  Value Value Value Value Value Value 
400000  19 24 39 49  59 79 
200000 39 49 79 99  119 159 
100000  79 99 159 199  239 319 
The numeric values above are available  when the SCL rising timing of the I2C bus is 0s. If the SCL rising timing 
of the I2C bus is late, the baud rate is set to the value later than the...

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4. I2C communication operation flowchart examples 
This section shows I2C communication operation flowchart examples. 
 I2C flowchart example (FIFO not used) when DMA mode is disabled 
(SSR:DMA=0) 
Figure 4-1 I2C flowchart example (FIFO not used) when DMA mode is disabled   
(SSR:DMA=0) 1/3 
Start
Initial settings:
Baud rate (BGR)
Slave address (ISBA)
Slave mask (ISMK)
I
2C enabling (ISMK:EN=1)
Master mode?
Write the send data. (TDR)Set the Master mode. (IBCR:MSS=1)...