Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
 
 If no acknowledgement response is sent while data is  received in slave mode due to the reserved address 
being detected, slave mode is released. In this case,  this bit is not set to 1 even if the next stop 
condition is detected. 

 When a read-modify-write instruction is issued, 1 is read. 
 
[bit 0] BB: Bus state bit 
This bit shows the bus state. 
The BB bit is set when: 
1.
 LOW is detected in SDA or SCL of the I2C bus. 
 
The BB bit is reset when: 
1.
 The stop...

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5.4.  Serial Status Register (SSR) 
The Serial Status Register (SSR) is used to check the transmission or reception state. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field REC TSET DMA TBIE ORE RDRFTDRETBI (IBSR) 
Attribute  R/W R/W R/W  R/W  R R  R R    
Initial 
value  0 0 0 0 0 0 1 1    
 
[bit 15] REC: Receive error flag clear bit 
This bit clears the ORE bit of Se rial Status Register (SSR). 

 If this bit is set to 1, the ORE bit is cleared. 

 This bit has no effect if...

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[bit 13] DMA: DMA mode enable bit 
This bit enables or disables DMA mode. 

 If this bit is set to 1, an interrupt condition is generated during DMA transfer. 

 If this bit is set to 0, an interrupt cond ition is generated during normal data transfer. 
 
Table 2-1. 
For details, see 
Bit Description 
0 Disables  DMA mode. 
1 Enables  DMA mode. 
 
 
This bit  state 

can be changed only when the ISMK:EN bit is 0. 
 
[bit 12] TBIE: Transmit bus idle interrupt enable bit...

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[bit 10] RDRF: Receive data full flag bit 
 This flag shows the state of Receive Data Register (RDR). 

 If the SMR:RIE bit and the receive data flag bit (RDR F) are 1, a receive interrupt request is issued. 

 When the receive data is loaded in  the RDR, this bit is set to 1. When data is read from the Receive 
Data Register (RDR), this bit is cleared to 0. 

 This bit is set at the falling edge of SCL signal (bit 8 of data). 

 This bit is also set even when a NACK...

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[bit 9] TDRE: Transmit data empty flag bit 
 This flag shows the state of Transmit Data Register (TDR). 

 If the SMR:TIE and TDRE bits are 1,  a Transmit Interrupt Request is output. 

 If transmit data is written in the TDR, this bit is set to 0 to indicate that the TDR contains valid data. 
When data is loaded to a shift register for transmission and its transmission is started, this bit is set to 1 
to indicate that the TDR does not have the valid data. 

 If the...

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5.5.  Receive Data Register/Transmit Data Register (RDR/TDR) 
The Receive and Transmit Data Registers are allocated at the same address. This register 
functions as the Receive Data Register when data is read from it. This register operates as 
the Tr

ansmit Data Register when data is written in it. 
 Receive Data Register (RDR) 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field  D7 D6 D5 D4 D3 D2 D1 D0 
Attribute        R R  R R R  R R R 
Initial 
value  0 
      0 0 0 0  0 0 0...

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 Transmit Data Register (TDR) 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field  D7 D6 D5 D4 D3 D2 D1 D0 
Attribute        W W  W W W  W W W 
Initial 
value      1 1 1 1 1 1 1 1 
 
The Transmit Data Register (TDR) is a data bu ffer register for serial data transmission. 

 Data of the Transmit Data register (TDR) is output to  the serial data line (SDA pin) with the MSB first 
order. 

 When the first byte is transmitted, the least signi ficant bit (TDR:D0) indicates the data...

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5.6.  7-bit Slave Address Mask Register (ISMK) 
The 7-bit Slave Address Mask Register (ISMK) is used to compare or set each bit of the slave 
address. 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field EN SM6 SM5 SM4  SM3 SM2 SM1 SM0 (ISBA) 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W    
Initial 
value  0 1 1 1 1 1 1 1    
 
[bit 15] EN: I2C interface operation enable bit 
This bit enables or disables the I2C interface operation. 
If set to 0: The I
2C interface operation is...

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5.7.  7-bit Slave Address Register (ISBA) 
The 7-bit Slave Address Register (ISBA) is used to set the slave address. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (ISMK) SAEN SA6 SA 5 SA4 SA3 SA2 SA1 SA0 
Attribute    R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] SAEN: Slave address enable bit 
This bit enables the slave address detection. 
If set to 0: The slave address is not detected. 
If set to 1: The ISBA and ISMK settings  and the received...

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5.8.  Baud Rate Generator Registers 1 and 0 (BGR1 and 
BGR0) 
Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency 
division ratio of serial clocks.   
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field - (BGR1) (BGR0) 
Attribute  - R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W  R/W R/WR/W
Initial 
value  - 
0 0 0 0 0 0  0 0 0  0 0 0 0 0 0 
 
The Baud Rate Generator Registers are used to set a frequency division ra tio of serial clocks. 
The BGR1...