Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
Figure 4-2 I2C flowchart example (FIFO not used) when DMA mode is disabled   
(SSR:DMA=0) 2/3 
Slave mode
IBSR:RSA=0?
IBSR:TRX=0?
IBSR:FBT=0?
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)
IBSR:RACK=0?
Write the send data. (TDR)
Set the waiting. (IBCR:WSEL)
Clear the interrupt flag. (IBCR:INT=0)
Clear the interrupt flag. (IBCR:INT=0) 
End
Yes
Yes Yes
No
No No
Yes
A
IBSR:FBT=1 ?
Yes
Read the received...

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Figure 4-3 I2C flowchart example (FIFO not used) when DMA mode is disabled   
(SSR:DMA=0) 3/3 
Reserved 
address
IBSR:FBT=1 ?
Multiple Master 
mode?
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL=1) Set an ACK. (IBCR:ACKE=1)
Clear the interrupt flag. (IBCR:INT=0)
A
Yes
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL) Set an ACK. (IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)
No
No
Yes
IBSR:TRX=1?
SSR:RDRF=1? 
Read the received data. (RDR)
Write the...

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 I2C flowchart examples (FIFO not used) when DMA mode is enabled 
(SSR:DMA=1) 
Figure 4-4 I2C flowchart example (FIFO not used) when DMA mode is enabled   
(SSR:DMA=1) 1/4 
Start
Initial settings:
Baud rate (BGR)
Slave address (ISBA)
Slave mask (ISMK)
I
2C enabling (ISMK:EN=1)
Master mode?
SSR:TBI=1?
Write the send data. (TDR)Set the Master mode. (IBCR:MSS=1)
IBCR:INT=1?
IBCR:BER=0?
IBCR:ACT=1?
IBCR:RSA=0?
A
Bus error processing
Arbitration Lost processing
End
Slave mode...

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Figure 4-5 I2C flowchart example (FIFO not used) when DMA mode is enabled   
(SSR:DMA=1) 2/4 
Master mode (TBI interrupt)
IBCR:TRX=1?
Completed to send?
Yes No
A
No
Yes
Read the received data. (RDR)
Completed to receive
Set the waiting. (IBCR:WSEL=1)
Set an ACK. (IBCR:ACKE=1)
Write the dummy data. (TDR)
NoWrite the send data. (TDR)
Set the waiting.
(IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
A
Start to iterate?
Write the send data . (TDR)
Set the iteration start .
(IBCR:MSS=SCC=1)...

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Figure 4-6 I2C flowchart example (FIFO not used) when DMA mode is enabled   
(SSR:DMA=1) 3/4 
Slave mode
IBCR:INT=1?
IBSR:TRX=0?
IBSR:FBT=0?
Set the waiting. (IBCR:WSEL)
Set an ACK. (IBCR:ACKE)
Clear the interrupt flag.
(IBCR:INT=0)
IBSR:RACK=0?
Read the received data. (RDR)
Write the send data. (TDR) 
Set the waiting. (IBCR:WSEL)
Clear the interrupt flag.
(IBCR: INT=0) 
IBSR:RSA=0?
SSR:RDRF=1?
A
Clear the interrupt flag.
(IBCR:INT=0)
End
IBSR:FBT=1?
Read the received data....

FUJITSU SEMICONDUCTOR LIMITED 
Figure 4-7 I2C flowchart example (FIFO not used) when DMA mode is enabled   
(SSR:DMA=1) 4/4 
Reserved 
address
IBSR:FBT=1 ?
Multiple Master  mode?
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL=1) Set an ACK. (IBCR:ACKE=1)
Clear the interrupt flag. (IBCR:INT=0)
A
Yes
Read the received data. (RDR)
Set the waiting. (IBCR:WSEL) Set an ACK. (IBCR:ACKE)
Clear the interrupt flag. (IBCR:INT=0)
No
No
Yes
IBSR:TRX=1?
SSR:RDRF=1? 
Read the received data. (RDR)
Write the...

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5. I2C Interface Registers 
The following lists the I2C interface registers. 
 List of I2C interface registers 
Table 5-1 List of I2C interface registers 
 bit 15                              bit 8 bit 7                               bit 0
IBCR (I2C Bus Control Register) SMR (Serial Mode Register) I2C 
IBSR (I
2C Bus Status Register) 
SSR (Serial Status Register) 
-  RDR/TDR (Transmit/Receive Data Register) 
BGR1 (Baud Rate Generator Register 1)  BGR0 (Baud Rate Generator...

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5.1. I2C Bus Control Register (IBCR) 
The I2C Bus Control Register (IBCR) is used to select master or slave mode, generate an 
iteration start condition, enable an acknowledgement, enable an interrupt, and display an 
interrupt flag. 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field MSS  ACT/ 
SCC  ACKE WSELCNDEINTEBER INT (SMR) 
Attribute 
R/W R/W R/W  R/W R/W R/W R R/W     
Initial 
value  0 0 0 0 0 0 0 0    
 
[bit 15] MSS: Master/slave select bit 
 If this bit is set to 1...

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 
 If DMA mode is disabled (SSR:DMA=0) and the MSS bit is set to 1, the MSS bit must be set to 0 
only when the MSS bit is 1 and the INT bit is 1. If  the MSS bit is set to 0 when the ACT bit is 1, 
the INT bit is also cleared to 0. 

 If DMA mode is enabled (SSR:DMA=1) and the MSS bit is set to 1, the MSS bit must be set to 0 
only when the MSS bit is 1 and the INT bit is 1, or  the SSR:TBI bit is 1. If the MSS bit is set to 0 
when the ACT bit is 1, the INT bit is also...

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 
 The SCC bit must be set to 1 during an interrupt of master mode (when MSS=1, ACT=1 and 
INT=1) only. If the SCC bit is set to 1 when th e ACT bit is 1, the INT bit is cleared to 0. 

 This bit must not be set to 1 in slave mode (when MSS=0 and ACT=1). 

 If the SCC bit is set to 1 and if the MSS bit is set to 0 simultaneously, the MSS bit setting is 
preceded. 

 When data is read by a read-modify-wr ite instruction, the SCC bit is read. 

 If both of the following...