Fujitsu Series 3 Manual

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5.9.  FIFO Control Register 1 (FCR1) 
The FIFO Control Register (FCR1) is used to set the FIFO test, select the transmit or receive 
FIFO, enable the transmit FIFO interrupt, and control the interrupt flag. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field FTST1 FTST0 - FLSTEFRIIEFDRQFTIE FSEL (FCR0) 
Attribute  R/W R/W  - R/W R/W  R/W R/W R/W    
Initial 
value  0 0 - 0 - 1 0 0    
 
[bit 15:14] FTST1, FTST0: FIFO test bits 
They are FIFO Test bits. 
They must always be set to 0....

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[bit 11] FRIIE: Receive FIFO idle detection enable bit 
This bit sets to detect the receive idle state if the receive FIFO contains  valid data and if it continues more 
than 8-bit hours. If the r eceive interrupt is enabled (SCR:RIE=1), a  receive interrupt is generated when the 
receive idle state is detected. 
If set to 0, a detection of receive idle state is disabled.   
If set to 1, a detection of receive idle state is enabled. 
Bit Description 
0  Disables the receive...

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[bit 9] FTIE: Transmit FIFO interrupt enable bit 
This bit enables a transmit FIFO interrupt. If this bit is set to 1, an interrupt occurs when the FDRQ bit is 
set to 1. 
Bit Description 
0  Disables the transmit FIFO interrupt. 
1  Enables the transmit FIFO interrupt. 
 
[bit 8] FSEL: FIFO buffer selection bit 
This bit selects the transmit or receive FIFO. 
If set to 0, transmit FIFO is assigned FIFO 1, and the receive FIFO is assigned FIFO2.   
If set to 1, transmit...

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5.10.  FIFO Control Register 0 (FCR0) 
The FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, 
save the read pointer, and set the data re-transmission. 
 bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (FCR1) - FLSTFLD FSETFCL2FCL1 FE2 FE1 
Attribute      -  R R/W  R/W R/W R/W  R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] Reserved bit 
When read, 0 is always read.   
When writing, always set to 0. 
 
[bit 6] FLST: FIFO re-transmit data...

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[bit 5] FLD: FIFO pointer reload bit 
This bit reloads the data, being saved in transmit FIFO by the FSET bit, to the reload pointer. This bit can be 
used to re-transmit data after a communication error or others have occurred.   
When the re-transmission setting has finished, this bit is set to 0. 
Bit Description 
0 Not  reloaded 
1 Reloaded 
 
 

 If this bit is 1, data is being reloaded in the read  pointer. Therefore, data writing except for FIFO reset 
is disabled....

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[bit 3] FCL2: FIFO2 reset bit 
This bit resets the FIFO2 value.   
If this bit is set to 1, the FIFO2 buffer is initialized.   
Only the FCR0:FLST bit is initialized, but the other bits of FCR1/0 registers are kept. 
Description Bit 
During writing During reading 
0 No  effect. 0 is always read. 
1  FIFO2 is reset. 
 
 

 Disable the FIFO2 operation first, and then reset the FIFO2 buffer. 

 Set the transmit FIFO interrupt enable bit to 0 before the execution. 

 The...

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[bit 1] FE2: FIFO2 operation enable bit 
This bit enables or disables the FIFO2 operation. 

 To use the FIFO2 operation, set this bit to 1. 

 If receive FIFO is selected by the FCR1:FSEL bit and if  a receive error has occurred, this bit is cleared to 
0. This bit cannot be set to 1 until the receive error is cleared. 

 To use FIFO2 as transmit FIFO, this bit must be  set to 1 or 0 when the transmit data is empty 
(SSR:TDRE=1). 

 To use FIFO2 as receive FIFO, this...

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[bit 0] FE1: FIFO1 operation enable bit 
This bit enables or disables the FIFO1 operation. 

 To use the FIFO1 operation, set this bit to 1. 

 If receive FIFO is selected by the FCR1:FSEL bit and if  a receive error has occurred, this bit is cleared to 
0. This bit cannot be set to 1 until the receive error is cleared. 

 To use FIFO1 as transmit FIFO, this bit must be  set to 1 or 0 when the transmit data is empty 
(SSR:TDRE=1). 

 To use FIFO1 as receive FIFO, this...

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5.11.  FIFO Byte Register (FBYTE) 
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. Also, 
this register can be used to generate a receive interrupt when certain number of data sets are 
received in the receive FIFO. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field (FBYTE2) (FBYTE1) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
The FBYTE register indicates the...

 
5. I2C Interface Registers 
 
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Chapter: I2C Interface (I2C Communications Control Interface) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  89 
FBYTE2, FBYTE1: FIFO2 data count display bit, FIFO1 data count display bit 
During writingSets the transfer data count. 
During reading Reads the effective count of data. 
 
Read (Effective data count) 
During transmission: The number of data sets alread y written in the FIFO buffer but not transmitted yet 
During reception: The number of...