Fujitsu Series 3 Manual

 
3. Operations of USB Function 
 
3.8.  STALL response/release of endpoint 0 
The STAL bit in the EP0 Control Register (EP0C) controls the STALL response and release of 
Endpoint 0. 
 STAL bit set timing 
To perform the STALL response, interpret the command  at the setup stage (SETP bit = 1 detection) of 
control transfer. If the STALL response  is required, set the STAL bit. (See Figure 3-18) After setting the 
STAL bit, clear th e in

terrupt cause (DRQO bit). 
Figure 3-18 STAL bit set timing...

 
3. Operations of USB Function 
 
 STAL bit clear timing 
Upon the detection of SETP bit = 1, pointing to the setup stage of control transfer, the STAL bit is 
automatically cleared and the STALL state is released. (See  Figure 3-19) 
Figure 3-19 STAL bit clear timing 
 
Token 
packetData 
packetHandshake  packet
Setup stage
Token 
packetData 
packetHandshake  packet
Data stage
DRQO bit
SETP bit
Idle period
STAL bit
  
 
  Upon th e d

etection of SETP bit = 1 (DRQO bit = 1 interru pt), the STAL bit is...

 
3. Operations of USB Function 
 
3.9.  Stall response/release of endpoints 1 to 5 
The STAL bit and the internal status bit in the EP1 to 5 Control Registers (EP1C to EP5C) 
controls the STALL response and release of Endpoints 1 to 5. 
 Stall response processed by software 
Figure 3-20  and Figure 3-21  shows the procedure to process the STALL response by software. To perform 
the STALL respon
se, configure the STAL bit of relevant  Endpoint by software. The internal status bit does 
not change then....

 
3. Operations of USB Function 
 
Figure 3-20 To process the STALL response by software (the STAL bit is cleared by software) 
UDCC.STALCLREN=0  
Host or hub
Internal status bitSTAL bit
0
Function macro
EPn (Endpoint n)
Software
Set the STAL 
bit to 1
0
IN/OUT token Function
10
11
Stall handshake
Data (for OUT)
IN/OUT token
Stall handshake
Data (for OUT)
Clear the 
STAL bit to 0
01
When a transaction occurs while 
the STAL bit is 1, the internal 
status bit is set to 1.
When the internal status bit is...

 
3. Operations of USB Function 
 
Figure 3-21 To process the STALL response by software (the STAL bit is cleared by hardware) 
UDCC.STALCLREN=1  
Host or hub
Internal status bitSTAL bit
0
Function macro
EPn (Endpoint n)
Software
Set the STAL 
bit to 1
0
IN/OUT token Function
10
11
Stall handshake
Data (for OUT)
IN/OUT token
Stall handshake
Data (for OUT)
11
When a transaction occurs 
while the STAL bit is 1, the 
internal status bit is set to 1.
When the internal status bit is 
1, the STALL response to...

 
3. Operations of USB Function 
 
 Automatic STALL response by hardware 
Figure 3-22  shows the procedure for the automatic STALL response by hardware. 
When the STALL  response is set by the Set Feature command, the hardware automatically set the internal 
status bit of the relevant Endpoint, irrespective of the STAL bit setting, and perform the STALL 
response.Once the internal bit is set, the value is  retained until cleared by the Clear Feature command from 
the host irrespective of the STAL bit...

 
4. Examples of USB Function Setting Procedures 
 
4.  Examples of USB Function Setting Procedures 
This section provides flowcharts for initialization, bus reset, CPU transfer, packet transfer 
(IN/OUT) and automatic data size transfer (IN/OUT). 
 Initialization 
 
Start
USBSet clock
USBEN.USBEN=1
UDCC.RST=1
D+Set pull-up disconnection
End
Set EP0C
Set EP1C to EP5C
UDCC.RST=0
EP0IS,EP0OS,EP1S to EP5S
BFINI=0
UDCC.HCONX=0
D+Set pull-up connection
Set UDCC.PWC
VBUS detected?NO
YES // Buffer clear //...

 
4. Examples of USB Function Setting Procedures 
 
 Bus reset 
 
USB interrupt
End
UDCS.BRST=1?
EP0IS,EP0OS,EP1S to EP5S
BFINI=1
NOUDCS.BRST=0
//  Buffer clear
YES
EP0IS,EP0OS,EP1S to EP5S
BFINI=0
  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-2: USB Function 
MN706-00002-1v0-E 
1102 
MB9Axxx/MB9Bxxx  Series  

 
4. Examples of USB Function Setting Procedures 
 
 Example control for CPU transfer 
 
Start USB interrupt
Check source
Write data to FIFO Read out data to FIFO
- USB data request bit (DRQ: bit 10 of the Epx 
Status Register (EPxS)) = 0Clear USB interrupt flag
- Dummy read of the releva nt USB interrupt control 
registerDummy read
End interrupt
OUT direction
IN direction
  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-2: USB Function 
MN706-00002-1v0-E 
1103 
MB9Axxx/MB9Bxxx  Series  

 
4. Examples of USB Function Setting Procedures 
 
 Example control for packet  transfer in IN direction 
 
[Initial settings]
[DMA transfer end interrupt]
Set interrupt level
(Resume the correlation 
between the USB interrupt 
level and the DMAC interrupt  level used by packet transfer  to that before the interrupt.)Set the next DMA transfer YES
NO
Start the next DMA transfer?
Disable USB interrupts to 
relevant Endpoint
Clear DMA transfer end interrupt
Clear USB interrupt flag +
Dummy read - USB data...