Fujitsu Series 3 Manual

 
4. Examples of USB Function Setting Procedures 
 
 Example control for packet  transfer in OUT direction 
 
[Initial settings]
Initial settings
- EP Control Register (EPxC) setting
- DRQIE:bit 14 of the EP Status Register (EPxS) = 1
End initial settings
[USB interrupt] Start USB interrupt
- Check by the SIZE bit of the Epx Status Register (EPxS)
NODMA transfer end flag = 1
YES
- USB data request bit (DRQ: bit 10 of the Epx 
Status Register (EPxS)) = 0 
- Dummy read of the relevant USB interrupt...

 
4. Examples of USB Function Setting Procedures 
 
 Example control for automatic data  size transfer in IN direction 
 
[Initial settings]
Initial settings
- EP Control Register (EPxC) setting- DMAE:bit 11 of the EP Control Register (EPxC) = 1
Notes:
Set USB interrupt level to the lowest
- DRQIE:bit 14 of the EP Status  Register (EPxS) = 1
End initial settings
[DMAtransfer end interrupt] Start DMA transfer end interrupt
End interrupt
Set interrupt level
(Resume the correlation between the  USB...

 
4. Examples of USB Function Setting Procedures 
 
 Example control for automatic data  size transfer in OUT direction 
 
[Initial settings]
Initial settings
- EP Control Register (EPxC) setting- DMAE:bit 11 of the EP Control Register (EPxC) = 1
Notes:
Set USB interrupt level to the lowest
End initial settings
[DMAtransfer end interrupt] Set DMAC
Set USB Endpoints
Set interrupt level
(Set USB interrupt level to the lowest)
Enable USB interrupts- DRQIE:bit 14 of the EP Status  Register (EPxS) = 1
Start...

 
5. USB Function Registers 
 
5.  USB Function Registers 
This section explains the configuration and functions of the registers used for the USB 
function. 
 USB function register list 
Abbreviation Register  name See 
UDCC UDC Control Register  5.1 
EP0C EP0 Control Register  5.2 
EP1C EP1 Control Register  5.3 
EP2C EP2 Control Register  5.3 
EP3C EP3 Control Register  5.3 
EP4C EP4 Control Register  5.3 
EP5C EP5 Control Register  5.3 
TMSP Time Stamp Register  5.4 
UDCS UDC Status Register  5.5...

 
5. USB Function Registers 
 
 UDCC.RST dependent register  bit update timing list 
 Register Bit 
FUJITSU SEMICONDUCTOR LIMITED 
UDCC HCONTX, PFBK, PWC 
EP0C PKS0 
Register bits to be updated when 
UDCC.RST=1 
EP1C EPEN, TYPE, DIR, PKS1 
EP2C EPEN, TYPE, DIR, PKS2 
EP3C EPEN, TYPE, DIR, PKS3 
EP4C EPEN, TYPE, DIR, PKS4 
EP5C EPEN, TYPE, DIR, 

PKS5 
EP0IS BFINI, DRQI Register bits initialized when 
UDCC.RST=1 EP0OS BFINI, DRQ, SPK 
EP1S BFINI, DRQ, SPK (Update when UDCC.RST=0) 
EP2S BFINI, DRQ, SPK...

 
5. USB Function Registers 
 
5.1.  UDC Control Register (UDCC) 
The UDC Control Register (UDCC) controls the UDC core circuit. 
The following figure shows the bit configuration of the UDC Control Register (UDCC). bit  15 14  13 12  11 10  9 8 
FUJITSU SEMICONDUCTOR LIMITED 
Field  Reserved Reserved ReservedReserv

edReserved Reserved Reserved Reserved
Attribute  - -  - - -  - - - 
Initial value 0 0  0 0 0  0 0 0 
  bit  7 6 5 4  3 2 1 0 
Field RST  RESUM HCONX USTP STALCLREN Reserved RFBK  PWC...

 
5. USB Function Registers 
 
[bit 6] RESUM:    Resume Setting Bit (RESUMe set) 
In suspend state while remote wake-up is enabled *,  the resume is started when writing 1 to the RESUM 
bit. To instruct to resume, set the RESUM bit to 1, and then write 0 to it to clear. 
* :  The DEVICE_REMOTE_WAKEUP bit is set by the SET_FEATURE command from the host. 
Bit Description 
0  Resets the USB resume start instruction bit 
1 Instructs to start the USB resume 
 
[bit 5] HCONX: Host Connection Bit (Host...

 
5. USB Function Registers 
 
[bit 3] STALCLREN: Endpoint 1 to 5 STAL Bit Clear Select Bit (STALl CLeaR Enable) 
This bit selects the method to clear the STAL bit of Endpoint 1 to Endpoint 5 using the Clear Feature 
command. The STALCLREN bit sets whether to automatically clear the STAL bit to 0 by hardware, a bit 
of EP1 to EP5 Control Registers (EP1C to EP5C) for Endpoints (1 to 5) specified by the Clear Feature 
command This bit selects the method to clear the STAL bit of the Endpoint Control...

 
5. USB Function Registers 
 
5.2.  EP0 Control Register (EP0C) 
The EP0 Control Register (EP0C) controls Endpoint 0. 
The following figure shows the bit configuration of the EP0 Control Register (EP0C). bit 15 14 13 12 11 10 9 8 
Field - - - - ReservedReserved STAL Reserved
Attribute  - - -  - - - R/W - 
Initial value  X X X  X 0 0  0 0 
  bit  7 6 5  4 3 2 1 0 
Field Reserved PKS0 
Attribute - R/W R/W  R/W R/W R/W  R/W R/W 
Initial value 0 1 0  0 0 0 0 0 
 
 
Except  bi

t 9 STAL, the EP0 Control...

 
5. USB Function Registers 
 
[bit 9] STAL: Endpoint 0 Stall Setting Bit (STALl ep0 set) This bit can set Endpoint 0 to the STALL state (STALL response). 
This bit is cleared by hardware. If  a SETUP packet is received by End point 0 after the STALL response to 
Endpoint 0 is performed, this bit is cleared to 0. For the timing to clear this bit, see    STAL bit clear 
ti ming
 of  3.8 STALL  res

ponse/release of endpoint 0. 
Bit Description 
0 Ignored 
1  Sets the STALL state (STALL response) 
 
 
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